标签:优先级 queue 不同 相同 asc smp 中断控制 mask 解释
本文主要分析mips64r2 PCI设备中断路由原理和irq号分配实现方法,并尝试回答如下问题:
本文主要分析PIC(可编程中断控制器)的工作原理,PIC一般集成在CPU中,不同arch、vendor CPU的PIC实现原理也不尽相同。本文基于kerne3.10 + mips64r2 XXX CPU分析。
如上图所示,硬件实现上,PCI中断路由主要涉及3个设备:PCI设备、PIC、CPU。
PIC作为核心器件,其核心功能如下:
3个主要中断信号:
软件实现上,抽象出2个表对象来实现中断路由的管理和处理:
如上图所示,中断由产生到结束的整个过程:
handle_int
-> plat_irq_dispatch
-> do_nlm_common_IRQ
-> do_IRQ
-> generic_handle_irq
-> generic_handle_irq_desc
-> __do_IRQ
-> handle_IRQ_event
硬件设备产生中断(request & pending);
IRT为PIC控制器的硬件表,主要在pic_init和request_irq中断注册时配置。IRT条目和字段解释如下:
IDT为软件表,主要在init_IRQ和request_irq中断注册时根据irq#配置IDT的相应条目的各个字段,如irq, irqaction handler, irq_chip handler等。2个配置过程区分如下:
#define NR_IRQS 64 struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = { [0 ... NR_IRQS-1] = { .status = IRQ_DISABLED, .chip = &no_irq_chip, .handle_irq = handle_bad_irq, .depth = 1, .lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock), } }; /** * struct irq_desc - interrupt descriptor * @irq: interrupt number for this descriptor * @timer_rand_state: pointer to timer rand state struct * @kstat_irqs: irq stats per cpu * @irq_2_iommu: iommu with this irq * @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()] * @chip: low level interrupt hardware access * @msi_desc: MSI descriptor * @handler_data: per-IRQ data for the irq_chip methods * @chip_data: platform-specific per-chip private data for the chip * methods, to allow shared chip implementations * @action: the irq action chain * @status: status information * @depth: disable-depth, for nested irq_disable() calls * @wake_depth: enable depth, for multiple set_irq_wake() callers * @irq_count: stats field to detect stalled irqs * @last_unhandled: aging timer for unhandled count * @irqs_unhandled: stats field for spurious unhandled interrupts * @lock: locking for SMP * @affinity: IRQ affinity on SMP * @node: node index useful for balancing * @pending_mask: pending rebalanced interrupts * @threads_active: number of irqaction threads currently running * @wait_for_threads: wait queue for sync_irq to wait for threaded handlers * @dir: /proc/irq/ procfs entry * @name: flow handler name for /proc/interrupts output */ struct irq_desc { unsigned int irq; struct timer_rand_state *timer_rand_state; unsigned int *kstat_irqs; #ifdef CONFIG_INTR_REMAP struct irq_2_iommu *irq_2_iommu; #endif irq_flow_handler_t handle_irq; struct irq_chip *chip; struct msi_desc *msi_desc; void *handler_data; void *chip_data; struct irqaction *action; /* IRQ action list */ unsigned int status; /* IRQ status */ unsigned int depth; /* nested irq disables */ unsigned int wake_depth; /* nested wake enables */ unsigned int irq_count; /* For detecting broken IRQs */ unsigned long last_unhandled; /* Aging timer for unhandled count */ unsigned int irqs_unhandled; spinlock_t lock; #ifdef CONFIG_SMP cpumask_var_t affinity; unsigned int node; #ifdef CONFIG_GENERIC_PENDING_IRQ cpumask_var_t pending_mask; #endif #endif atomic_t threads_active; #ifdef CONFIG_PREEMPT_HARDIRQS unsigned long forced_threads_active; #endif wait_queue_head_t wait_for_threads; #ifdef CONFIG_PROC_FS struct proc_dir_entry *dir; #endif const char *name; } ____cacheline_internodealigned_in_smp; struct irq_chip { const char *name; unsigned int (*startup)(unsigned int irq); void (*shutdown)(unsigned int irq); void (*enable)(unsigned int irq); void (*disable)(unsigned int irq); void (*ack)(unsigned int irq); void (*mask)(unsigned int irq); void (*mask_ack)(unsigned int irq); void (*unmask)(unsigned int irq); void (*eoi)(unsigned int irq); void (*end)(unsigned int irq); int (*set_affinity)(unsigned int irq, const struct cpumask *dest); int (*retrigger)(unsigned int irq); int (*set_type)(unsigned int irq, unsigned int flow_type); int (*set_wake)(unsigned int irq, unsigned int on); void (*bus_lock)(unsigned int irq); void (*bus_sync_unlock)(unsigned int irq); /* Currently used only by UML, might disappear one day.*/ #ifdef CONFIG_IRQ_RELEASE_METHOD void (*release)(unsigned int irq, void *dev_id); #endif /* * For compatibility, ->typename is copied into ->name. * Will disappear. */ const char *typename; }; static struct irq_chip nlm_common_pic = { .unmask = pic_unmask, .mask = pic_shutdown, .ack = pic_ack, .end = pic_end, .set_affinity = pic_set_affinity };
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标签:优先级 queue 不同 相同 asc smp 中断控制 mask 解释
原文地址:http://www.cnblogs.com/wahaha02/p/6128969.html