标签：cal void dev sms date eterm attr compile rate
COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE NINTH EDITION
Software cache coherence schemes attempt to avoid the need for additional hard-
ware circuitry and logic by relying on the compiler and operating system to deal with
the problem. Software approaches are attractive because the overhead of detecting
potential problems is transferred from run time to compile time, and the design
complexity is transferred from hardware to software. On the other hand, compile-
time software approaches generally must make conservative decisions, leading to
inefficient cache utilization.
Compiler-based coherence mechanisms perform an analysis on the code to
determine which data items may become unsafe for caching, and they mark those
items accordingly. The operating system or hardware then prevents noncacheable
items from being cached.
The simplest approach is to prevent any shared data variables from being
cached. This is too conservative, because a shared data structure may be exclusively
used during some periods and may be effectively read-only during other periods. It
is only during periods when at least one process may update the variable and at least
one other process may access the variable that cache coherence is an issue.
More efficient approaches analyze the code to determine safe periods for
shared variables. The compiler then inserts instructions into the generated code
to enforce cache coherence during the critical periods. A number of techniques
have been developed for performing the analysis and for enforcing the results; see
[LILJ93] and [STEN90] for surveys.
Software Solutions CACHE COHERENCE AND THE MESI PROTOCOL
标签：cal void dev sms date eterm attr compile rate
原文地址：http://www.cnblogs.com/yuanjiangw/p/6252410.html
