Signal in unit is connected to following multiple drivers VHDL

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参考链接

https://blog.csdn.net/jbb0523/article/details/6946899

出错原因

两个Process都对LDS_temp进行了赋值，万一在某个时刻，在两个Process中对LDS_temp赋值条件都满足，那么你让FPGA该怎么做呢？让它听谁哪个Process块的呢？

报错

ISE14.7 综合时报错

ERROR:HDLCompiler:1401 - "D:\project\ISEProject\FlowingLED\LED.vhd" Line 23: Signal LDS_temp[7] in unit LED is connected to following multiple drivers:
Driver 0: output signal LDS_temp[7] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[7] of instance Latch (LDS_temp[7]).
Driver 0: output signal LDS_temp[6] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[6] of instance Latch (LDS_temp[6]).
Driver 0: output signal LDS_temp[5] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[5] of instance Latch (LDS_temp[5]).
Driver 0: output signal LDS_temp[4] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[4] of instance Latch (LDS_temp[4]).
Driver 0: output signal LDS_temp[3] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[3] of instance Latch (LDS_temp[3]).
Driver 0: output signal LDS_temp[2] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[2] of instance Latch (LDS_temp[2]).
Driver 0: output signal LDS_temp[1] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[1] of instance Latch (LDS_temp[1]).
Driver 0: output signal LDS_temp[0] of instance Flip-flop (LDS_temp).
Driver 1: output signal LDS_temp[0] of instance Latch (LDS_temp[0]).
--> 

出错代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Flowing LED
-- 先分频再移位
entity LED is
    port(
    GCLK,BTNU:in std_logic;
    LDS:out std_logic_vector(7 downto 0)
    );
end LED;


architecture Behavioral of LED is
-- 计数
signal count:std_logic_vector(25 downto 0);
signal clk_temp:std_logic;
signal Q_temp:std_logic;
signal LDS_temp:std_logic_vector(7 downto 0):="00000001";
begin

    process(GCLK,BTNU)  
    --分频系数
    variable N :std_logic_vector(25 downto 0):="10111110101111000010000000";
    begin  
        if BTNU='1' then
            count<="00000000000000000000000001"; 
            clk_temp<='1';  
            LDS_temp<= "00000001";
        elsif (GCLK'EVENT and GCLK='1')then 
            if (count=N)then
                count<="00000000000000000000000001";
                clk_temp<='1';
            else
                count<=count+1;
                clk_temp<='0';
            end if;
        end if;
    end process;
    --得到的clk_temp为2Hz，占空比1/50000000
    
    process(clk_temp)
    begin
        if (clk_temp'EVENT and clk_temp='1')then
            LDS_temp(7)<=Q_temp;
            LDS_temp(6 downto 0)<=LDS_temp(7 downto 1);
            --Q_temp<=LDS_temp(0);
        end if;
    end process;
    LDS<=LDS_temp;
end Behavioral;

Signal in unit is connected to following multiple drivers VHDL

标签：lse   logic   rar   put   project   ieee   nec   entity   RoCE   

原文地址：https://www.cnblogs.com/uestcman/p/10326299.html