标签：des style blog http io ar for sp 2014
The 8253 was used in IBM PC compatibles since their introduction in 1981.[1] In modern times, this PIT is not included as a separate chip in an x86 PC. Rather, its functionality is included as part of the motherboard‘s southbridge chipset. In some modern chipsets, this change may show up as measurable timing differences in accessing a PIT using the x86 I/O address space. Reads and writes to such a PIT‘s registers in the I/O address space may complete much faster.
Newer motherboards also include a counter through the Advanced Configuration and Power Interface (ACPI), a counter on the Local Advanced Programmable Interrupt Controller (Local APIC), and a High Precision Event Timer. The CPU itself also provides the Time Stamp Counter (TSC) facility.
来自 <http://en.wikipedia.org/wiki/Intel_8253>
The timer has three counters, called channels. Each channel can be programmed to operate in one of six modes. Once programmed, the channels can perform their tasks independently. The timer is usually assigned to IRQ-0 (highest priority hardware interrupt) because of the critical function it performs and because so many devices depend on it.[
来自 <http://en.wikipedia.org/wiki/Intel_8253>
标签：des style blog http io ar for sp 2014
原文地址：http://www.cnblogs.com/lixiaomao/p/4045770.html
