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1. 网口硬件方案：
AT91SAM9G10 + DM9000CEP；
DM9000CEP为MAC+PHY解决方案，与MCU链接通过8位或16位数据总线。
内部SRAM为16Kbyte。
2. DM9000CEP硬件接口（略）。
3. DM9000CEP寄存器。
DM9000CEP包含两类寄存器：控制状态寄存器（CSRs）和PHY寄存器。
访问PHY寄存器是通过访问CSRs实现的，相关寄存器有：
1) EPCR：EEPROm&PHY Control Register.
2) EPAR : EEPROM & PHY Address Register.
3) EPDRL: EEPROM & PHY Low Byte Data Register.
4) EPDRH: EEPROM & PHY High Byte Data Register.
此外注意：CSRs中包含MAC地址寄存器：PAR：Physical Address Register.
要发送数据必须填写MAC地址。
4. DM9000CEP数据交互。
DM9000CEP数据和地址共用数据总线，通过CMD线选择。
更准确的说法是：
There are only two addressing ports through the access of the host interface.
One port is the INDEX port and the other is the DATA port.
The INDEX port is decoded by the pin CMD =0 and the DATA port by the pin CMD =1.
The contents of the INDEX port are the register address of the DATA port.
Before the access of any register, the address of the register must be saved in the INDEX port.
创意发生了：
数据（DATA port）或地址（INDEX port）都是通过8位或16位数据总线访问，
在操作总线时同时操作CMD，要把CMD当作普通GPIO控制吗？
CPU要访问网口DM9000CEP，首先要选中该芯片，通过SMC片选CS2或CS4，
CS2地址0x30000000，CS4地址0x50000000。
操作该芯片时，首先选中该芯片，然后控制CMD电平，然后操作数据总线。
这样明显增加了一步，访问速度变慢：我们可以在操作地址的同时操作CMD电平，
即操作地址总线，同时操作数据总线。如选择A2为CMD控制线，访问DATA port，
地址为0x30000004，访问INDEX port，地址为0x30000000。
地址线选取原则：>=A2，偶数地址线。
#define DM9000_IO CONFIG_DM9000_BASE //0x30000000 ;INDEX port
#define DM9000_DATA (CONFIG_DM9000_BASE + 0x04) //0x30000004 ;DATA port.
5. 数据收发。
The internal memory size is 16K bytes. The first location of 3K bytes is used for the data buffer of the
packet transmission. The other 13K bytes are used for the buffer of the receiving packets. So in the write
memory operation, when the bit 7 of IMR is set, the memory address increment will wrap to location 0 if
the end of address (i.e. 3K) is reached. In a similar way, in the read memory operation, when the bit 7 of
IMR is set, the memory address increment will wrap to location 0x0C00 if the end of address (i.e. 16K) is
reached.
数据发送：两包数据循环发送。
There are two packets, sequentially named as index I and index II, can be stored in the TX SRAM at the
same time. The index register 02h controls the insertion of CRC and pads. Their statuses are
recorded at index registers 03h and 04h respectively The start address of transmission is 00h and the
current packet is index I after software or hardware reset. Firstly write data to the TX SRAM using the
DMA port and then write the byte count to byte_ count register at index register 0fch and 0fdh. Set the bit 1 of
control register. The DM9000C starts to transmit the index I packet. Before the transmission of the index I
packet ends, the data of the next (index II) packet can be moved to TX SRAM. After the index I packet ends
the transmission, write the byte count data of the Index II to BYTE_COUNT register and then set the bit
1 of control register to transmit the index II packet. The following packets, named index I, II, I, II,..., use
the same way to be transmitted.
数据接收：循环发送
The RX SRAM is a ring data structure. The start address of RX SRAM is 0C00h after software or
hardware reset. Each packet has a 4-byte header followed with the data of the reception packet which
CRC field is included. The format of the 4-byte header is 01h, status, BYTE_COUNT low and
BYTE_COUNT high. It is noted that the start address of each packet is in the proper address boundary
which depends on the operation mode (the 8-bit or 16-bit ).
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原文地址：http://www.cnblogs.com/embedded-linux/p/4830645.html
