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1 // DSP48A1 : In order to incorporate this function into the design, 2 // Verilog : the following instance declaration needs to be placed 3 // instance : in the body of the design code. The instance name 4 // declaration : (DSP48A1_inst) and/or the port declarations within the 5 // code : parenthesis may be changed to properly reference and 6 // : connect this function to the design. All inputs 7 // : and outputs must be connected. 8 9 // <-----Cut code below this line----> 10 11 // DSP48A1: 48-bit Multi-Functional Arithmetic Block 12 // Spartan-6 13 // Xilinx HDL Language Template, version 14.7 14 15 DSP48A1 #( 16 .A0REG(0), // First stage A input pipeline register (0/1) 17 .A1REG(1), // Second stage A input pipeline register (0/1) 18 .B0REG(0), // First stage B input pipeline register (0/1) 19 .B1REG(1), // Second stage B input pipeline register (0/1) 20 .CARRYINREG(1), // CARRYIN input pipeline register (0/1) 21 .CARRYINSEL("OPMODE5"), // Specify carry-in source, "CARRYIN" or "OPMODE5" 22 .CARRYOUTREG(1), // CARRYOUT output pipeline register (0/1) 23 .CREG(1), // C input pipeline register (0/1) 24 .DREG(1), // D pre-adder input pipeline register (0/1) 25 .MREG(1), // M pipeline register (0/1) 26 .OPMODEREG(1), // Enable=1/disable=0 OPMODE input pipeline registers 27 .PREG(1), // P output pipeline register (0/1) 28 .RSTTYPE("SYNC") // Specify reset type, "SYNC" or "ASYNC" 29 ) 30 DSP48A1_inst ( 31 // Cascade Ports: 18-bit (each) output: Ports to cascade from one DSP48 to another 32 .BCOUT(BCOUT), // 18-bit output: B port cascade output 33 .PCOUT(PCOUT), // 48-bit output: P cascade output (if used, connect to PCIN of another DSP48A1) 34 // Data Ports: 1-bit (each) output: Data input and output ports 35 .CARRYOUT(CARRYOUT), // 1-bit output: carry output (if used, connect to CARRYIN pin of another 36 // DSP48A1) 37 38 .CARRYOUTF(CARRYOUTF), // 1-bit output: fabric carry output 39 .M(M), // 36-bit output: fabric multiplier data output 40 .P(P), // 48-bit output: data output 41 // Cascade Ports: 48-bit (each) input: Ports to cascade from one DSP48 to another 42 .PCIN(PCIN), // 48-bit input: P cascade input (if used, connect to PCOUT of another DSP48A1) 43 // Control Input Ports: 1-bit (each) input: Clocking and operation mode 44 .CLK(CLK), // 1-bit input: clock input 45 .OPMODE(OPMODE), // 8-bit input: operation mode input 46 // Data Ports: 18-bit (each) input: Data input and output ports 47 .A(A), // 18-bit input: A data input 48 .B(B), // 18-bit input: B data input (connected to fabric or BCOUT of adjacent DSP48A1) 49 .C(C), // 48-bit input: C data input 50 .CARRYIN(CARRYIN), // 1-bit input: carry input signal (if used, connect to CARRYOUT pin of another 51 // DSP48A1) 52 53 .D(D), // 18-bit input: B pre-adder data input 54 // Reset/Clock Enable Input Ports: 1-bit (each) input: Reset and enable input ports 55 .CEA(CEA), // 1-bit input: active high clock enable input for A registers 56 .CEB(CEB), // 1-bit input: active high clock enable input for B registers 57 .CEC(CEC), // 1-bit input: active high clock enable input for C registers 58 .CECARRYIN(CECARRYIN), // 1-bit input: active high clock enable input for CARRYIN registers 59 .CED(CED), // 1-bit input: active high clock enable input for D registers 60 .CEM(CEM), // 1-bit input: active high clock enable input for multiplier registers 61 .CEOPMODE(CEOPMODE), // 1-bit input: active high clock enable input for OPMODE registers 62 .CEP(CEP), // 1-bit input: active high clock enable input for P registers 63 .RSTA(RSTA), // 1-bit input: reset input for A pipeline registers 64 .RSTB(RSTB), // 1-bit input: reset input for B pipeline registers 65 .RSTC(RSTC), // 1-bit input: reset input for C pipeline registers 66 .RSTCARRYIN(RSTCARRYIN), // 1-bit input: reset input for CARRYIN pipeline registers 67 .RSTD(RSTD), // 1-bit input: reset input for D pipeline registers 68 .RSTM(RSTM), // 1-bit input: reset input for M pipeline registers 69 .RSTOPMODE(RSTOPMODE), // 1-bit input: reset input for OPMODE pipeline registers 70 .RSTP(RSTP) // 1-bit input: reset input for P pipeline registers 71 ); 72 73 // End of DSP48A1_inst instantiation 74 75 76 // PLL_BASE : In order to incorporate this function into the design, 77 // Verilog : the following instance declaration needs to be placed 78 // instance : in the body of the design code. The instance name 79 // declaration : (PLL_BASE_inst) and/or the port declarations within the 80 // code : parenthesis may be changed to properly reference and 81 // : connect this function to the design. All inputs 82 // : and outputs must be connected. 83 84 // <-----Cut code below this line----> 85 86 // PLL_BASE: Phase Locked Loop (PLL) Clock Management Component 87 // Spartan-6 88 // Xilinx HDL Language Template, version 14.7 89 90 PLL_BASE #( 91 .BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED" 92 .CLKFBOUT_MULT(1), // Multiply value for all CLKOUT clock outputs (1-64) 93 .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of the clock feedback output (0.0-360.0). 94 .CLKIN_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 95 // MHz). 96 // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128) 97 .CLKOUT0_DIVIDE(1), 98 .CLKOUT1_DIVIDE(1), 99 .CLKOUT2_DIVIDE(1), 100 .CLKOUT3_DIVIDE(1), 101 .CLKOUT4_DIVIDE(1), 102 .CLKOUT5_DIVIDE(1), 103 // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99). 104 .CLKOUT0_DUTY_CYCLE(0.5), 105 .CLKOUT1_DUTY_CYCLE(0.5), 106 .CLKOUT2_DUTY_CYCLE(0.5), 107 .CLKOUT3_DUTY_CYCLE(0.5), 108 .CLKOUT4_DUTY_CYCLE(0.5), 109 .CLKOUT5_DUTY_CYCLE(0.5), 110 // CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0). 111 .CLKOUT0_PHASE(0.0), 112 .CLKOUT1_PHASE(0.0), 113 .CLKOUT2_PHASE(0.0), 114 .CLKOUT3_PHASE(0.0), 115 .CLKOUT4_PHASE(0.0), 116 .CLKOUT5_PHASE(0.0), 117 .CLK_FEEDBACK("CLKFBOUT"), // Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0") 118 .COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL" 119 .DIVCLK_DIVIDE(1), // Division value for all output clocks (1-52) 120 .REF_JITTER(0.1), // Reference Clock Jitter in UI (0.000-0.999). 121 .RESET_ON_LOSS_OF_LOCK("FALSE") // Must be set to FALSE 122 ) 123 PLL_BASE_inst ( 124 .CLKFBOUT(CLKFBOUT), // 1-bit output: PLL_BASE feedback output 125 // CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs 126 .CLKOUT0(CLKOUT0), 127 .CLKOUT1(CLKOUT1), 128 .CLKOUT2(CLKOUT2), 129 .CLKOUT3(CLKOUT3), 130 .CLKOUT4(CLKOUT4), 131 .CLKOUT5(CLKOUT5), 132 .LOCKED(LOCKED), // 1-bit output: PLL_BASE lock status output 133 .CLKFBIN(CLKFBIN), // 1-bit input: Feedback clock input 134 .CLKIN(CLKIN), // 1-bit input: Clock input 135 .RST(RST) // 1-bit input: Reset input 136 ); 137 138 // End of PLL_BASE_inst instantiation 139 140 141 // DCM_CLKGEN : In order to incorporate this function into the design, 142 // Verilog : the following instance declaration needs to be placed 143 // instance : in the body of the design code. The instance name 144 // declaration : (DCM_CLKGEN_inst) and/or the port declarations within the 145 // code : parenthesis may be changed to properly reference and 146 // : connect this function to the design. All inputs 147 // : and outputs must be connected. 148 149 // <-----Cut code below this line----> 150 151 // DCM_CLKGEN: Frequency Aligned Digital Clock Manager 152 // Spartan-6 153 // Xilinx HDL Language Template, version 14.7 154 155 DCM_CLKGEN #( 156 .CLKFXDV_DIVIDE(2), // CLKFXDV divide value (2, 4, 8, 16, 32) 157 .CLKFX_DIVIDE(1), // Divide value - D - (1-256) 158 .CLKFX_MD_MAX(0.0), // Specify maximum M/D ratio for timing anlysis 159 .CLKFX_MULTIPLY(4), // Multiply value - M - (2-256) 160 .CLKIN_PERIOD(0.0), // Input clock period specified in nS 161 .SPREAD_SPECTRUM("NONE"), // Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD", 162 // "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2" 163 .STARTUP_WAIT("FALSE") // Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE) 164 ) 165 DCM_CLKGEN_inst ( 166 .CLKFX(CLKFX), // 1-bit output: Generated clock output 167 .CLKFX180(CLKFX180), // 1-bit output: Generated clock output 180 degree out of phase from CLKFX. 168 .CLKFXDV(CLKFXDV), // 1-bit output: Divided clock output 169 .LOCKED(LOCKED), // 1-bit output: Locked output 170 .PROGDONE(PROGDONE), // 1-bit output: Active high output to indicate the successful re-programming 171 .STATUS(STATUS), // 2-bit output: DCM_CLKGEN status 172 .CLKIN(CLKIN), // 1-bit input: Input clock 173 .FREEZEDCM(FREEZEDCM), // 1-bit input: Prevents frequency adjustments to input clock 174 .PROGCLK(PROGCLK), // 1-bit input: Clock input for M/D reconfiguration 175 .PROGDATA(PROGDATA), // 1-bit input: Serial data input for M/D reconfiguration 176 .PROGEN(PROGEN), // 1-bit input: Active high program enable 177 .RST(RST) // 1-bit input: Reset input pin 178 ); 179 180 // End of DCM_CLKGEN_inst instantiation 181 182 183 // DCM_SP : In order to incorporate this function into the design, 184 // Verilog : the following instance declaration needs to be placed 185 // instance : in the body of the design code. The instance name 186 // declaration : (DCM_SP_inst) and/or the port declarations within the 187 // code : parenthesis may be changed to properly reference and 188 // : connect this function to the design. All inputs 189 // : and outputs must be connected. 190 191 // <-----Cut code below this line----> 192 193 // DCM_SP: Digital Clock Manager 194 // Spartan-6 195 // Xilinx HDL Language Template, version 14.7 196 197 DCM_SP #( 198 .CLKDV_DIVIDE(2.0), // CLKDV divide value 199 // (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16). 200 .CLKFX_DIVIDE(1), // Divide value on CLKFX outputs - D - (1-32) 201 .CLKFX_MULTIPLY(4), // Multiply value on CLKFX outputs - M - (2-32) 202 .CLKIN_DIVIDE_BY_2("FALSE"), // CLKIN divide by two (TRUE/FALSE) 203 .CLKIN_PERIOD(10.0), // Input clock period specified in nS 204 .CLKOUT_PHASE_SHIFT("NONE"), // Output phase shift (NONE, FIXED, VARIABLE) 205 .CLK_FEEDBACK("1X"), // Feedback source (NONE, 1X, 2X) 206 .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS 207 .DFS_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value 208 .DLL_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value 209 .DSS_MODE("NONE"), // Unsupported - Do not change value 210 .DUTY_CYCLE_CORRECTION("TRUE"), // Unsupported - Do not change value 211 .FACTORY_JF(16‘hc080), // Unsupported - Do not change value 212 .PHASE_SHIFT(0), // Amount of fixed phase shift (-255 to 255) 213 .STARTUP_WAIT("FALSE") // Delay config DONE until DCM_SP LOCKED (TRUE/FALSE) 214 ) 215 DCM_SP_inst ( 216 .CLK0(CLK0), // 1-bit output: 0 degree clock output 217 .CLK180(CLK180), // 1-bit output: 180 degree clock output 218 .CLK270(CLK270), // 1-bit output: 270 degree clock output 219 .CLK2X(CLK2X), // 1-bit output: 2X clock frequency clock output 220 .CLK2X180(CLK2X180), // 1-bit output: 2X clock frequency, 180 degree clock output 221 .CLK90(CLK90), // 1-bit output: 90 degree clock output 222 .CLKDV(CLKDV), // 1-bit output: Divided clock output 223 .CLKFX(CLKFX), // 1-bit output: Digital Frequency Synthesizer output (DFS) 224 .CLKFX180(CLKFX180), // 1-bit output: 180 degree CLKFX output 225 .LOCKED(LOCKED), // 1-bit output: DCM_SP Lock Output 226 .PSDONE(PSDONE), // 1-bit output: Phase shift done output 227 .STATUS(STATUS), // 8-bit output: DCM_SP status output 228 .CLKFB(CLKFB), // 1-bit input: Clock feedback input 229 .CLKIN(CLKIN), // 1-bit input: Clock input 230 .DSSEN(DSSEN), // 1-bit input: Unsupported, specify to GND. 231 .PSCLK(PSCLK), // 1-bit input: Phase shift clock input 232 .PSEN(PSEN), // 1-bit input: Phase shift enable 233 .PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement input 234 .RST(RST) // 1-bit input: Active high reset input 235 ); 236 237 // End of DCM_SP_inst instantiation 238 239 240 // RAMB16BWER : In order to incorporate this function into the design, 241 // Verilog : the following instance declaration needs to be placed 242 // instance : in the body of the design code. The instance name 243 // declaration : (RAMB16BWER_inst) and/or the port declarations within the 244 // code : parenthesis may be changed to properly reference and 245 // : connect this function to the design. All inputs 246 // : and outputs must be connected. 247 248 // <-----Cut code below this line----> 249 250 // RAMB16BWER: 16k-bit Data and 2k-bit Parity Configurable Synchronous Dual Port Block RAM with Optional Output Registers 251 // Spartan-6 252 // Xilinx HDL Language Template, version 14.7 253 254 RAMB16BWER #( 255 // DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36 256 .DATA_WIDTH_A(0), 257 .DATA_WIDTH_B(0), 258 // DOA_REG/DOB_REG: Optional output register (0 or 1) 259 .DOA_REG(0), 260 .DOB_REG(0), 261 // EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST 262 .EN_RSTRAM_A("TRUE"), 263 .EN_RSTRAM_B("TRUE"), 264 // INITP_00 to INITP_07: Initial memory contents. 265 .INITP_00(256‘h0000000000000000000000000000000000000000000000000000000000000000), 266 .INITP_01(256‘h0000000000000000000000000000000000000000000000000000000000000000), 267 .INITP_02(256‘h0000000000000000000000000000000000000000000000000000000000000000), 268 .INITP_03(256‘h0000000000000000000000000000000000000000000000000000000000000000), 269 .INITP_04(256‘h0000000000000000000000000000000000000000000000000000000000000000), 270 .INITP_05(256‘h0000000000000000000000000000000000000000000000000000000000000000), 271 .INITP_06(256‘h0000000000000000000000000000000000000000000000000000000000000000), 272 .INITP_07(256‘h0000000000000000000000000000000000000000000000000000000000000000), 273 // INIT_00 to INIT_3F: Initial memory contents. 274 .INIT_00(256‘h0000000000000000000000000000000000000000000000000000000000000000), 275 .INIT_01(256‘h0000000000000000000000000000000000000000000000000000000000000000), 276 .INIT_02(256‘h0000000000000000000000000000000000000000000000000000000000000000), 277 .INIT_03(256‘h0000000000000000000000000000000000000000000000000000000000000000), 278 .INIT_04(256‘h0000000000000000000000000000000000000000000000000000000000000000), 279 .INIT_05(256‘h0000000000000000000000000000000000000000000000000000000000000000), 280 .INIT_06(256‘h0000000000000000000000000000000000000000000000000000000000000000), 281 .INIT_07(256‘h0000000000000000000000000000000000000000000000000000000000000000), 282 .INIT_08(256‘h0000000000000000000000000000000000000000000000000000000000000000), 283 .INIT_09(256‘h0000000000000000000000000000000000000000000000000000000000000000), 284 .INIT_0A(256‘h0000000000000000000000000000000000000000000000000000000000000000), 285 .INIT_0B(256‘h0000000000000000000000000000000000000000000000000000000000000000), 286 .INIT_0C(256‘h0000000000000000000000000000000000000000000000000000000000000000), 287 .INIT_0D(256‘h0000000000000000000000000000000000000000000000000000000000000000), 288 .INIT_0E(256‘h0000000000000000000000000000000000000000000000000000000000000000), 289 .INIT_0F(256‘h0000000000000000000000000000000000000000000000000000000000000000), 290 .INIT_10(256‘h0000000000000000000000000000000000000000000000000000000000000000), 291 .INIT_11(256‘h0000000000000000000000000000000000000000000000000000000000000000), 292 .INIT_12(256‘h0000000000000000000000000000000000000000000000000000000000000000), 293 .INIT_13(256‘h0000000000000000000000000000000000000000000000000000000000000000), 294 .INIT_14(256‘h0000000000000000000000000000000000000000000000000000000000000000), 295 .INIT_15(256‘h0000000000000000000000000000000000000000000000000000000000000000), 296 .INIT_16(256‘h0000000000000000000000000000000000000000000000000000000000000000), 297 .INIT_17(256‘h0000000000000000000000000000000000000000000000000000000000000000), 298 .INIT_18(256‘h0000000000000000000000000000000000000000000000000000000000000000), 299 .INIT_19(256‘h0000000000000000000000000000000000000000000000000000000000000000), 300 .INIT_1A(256‘h0000000000000000000000000000000000000000000000000000000000000000), 301 .INIT_1B(256‘h0000000000000000000000000000000000000000000000000000000000000000), 302 .INIT_1C(256‘h0000000000000000000000000000000000000000000000000000000000000000), 303 .INIT_1D(256‘h0000000000000000000000000000000000000000000000000000000000000000), 304 .INIT_1E(256‘h0000000000000000000000000000000000000000000000000000000000000000), 305 .INIT_1F(256‘h0000000000000000000000000000000000000000000000000000000000000000), 306 .INIT_20(256‘h0000000000000000000000000000000000000000000000000000000000000000), 307 .INIT_21(256‘h0000000000000000000000000000000000000000000000000000000000000000), 308 .INIT_22(256‘h0000000000000000000000000000000000000000000000000000000000000000), 309 .INIT_23(256‘h0000000000000000000000000000000000000000000000000000000000000000), 310 .INIT_24(256‘h0000000000000000000000000000000000000000000000000000000000000000), 311 .INIT_25(256‘h0000000000000000000000000000000000000000000000000000000000000000), 312 .INIT_26(256‘h0000000000000000000000000000000000000000000000000000000000000000), 313 .INIT_27(256‘h0000000000000000000000000000000000000000000000000000000000000000), 314 .INIT_28(256‘h0000000000000000000000000000000000000000000000000000000000000000), 315 .INIT_29(256‘h0000000000000000000000000000000000000000000000000000000000000000), 316 .INIT_2A(256‘h0000000000000000000000000000000000000000000000000000000000000000), 317 .INIT_2B(256‘h0000000000000000000000000000000000000000000000000000000000000000), 318 .INIT_2C(256‘h0000000000000000000000000000000000000000000000000000000000000000), 319 .INIT_2D(256‘h0000000000000000000000000000000000000000000000000000000000000000), 320 .INIT_2E(256‘h0000000000000000000000000000000000000000000000000000000000000000), 321 .INIT_2F(256‘h0000000000000000000000000000000000000000000000000000000000000000), 322 .INIT_30(256‘h0000000000000000000000000000000000000000000000000000000000000000), 323 .INIT_31(256‘h0000000000000000000000000000000000000000000000000000000000000000), 324 .INIT_32(256‘h0000000000000000000000000000000000000000000000000000000000000000), 325 .INIT_33(256‘h0000000000000000000000000000000000000000000000000000000000000000), 326 .INIT_34(256‘h0000000000000000000000000000000000000000000000000000000000000000), 327 .INIT_35(256‘h0000000000000000000000000000000000000000000000000000000000000000), 328 .INIT_36(256‘h0000000000000000000000000000000000000000000000000000000000000000), 329 .INIT_37(256‘h0000000000000000000000000000000000000000000000000000000000000000), 330 .INIT_38(256‘h0000000000000000000000000000000000000000000000000000000000000000), 331 .INIT_39(256‘h0000000000000000000000000000000000000000000000000000000000000000), 332 .INIT_3A(256‘h0000000000000000000000000000000000000000000000000000000000000000), 333 .INIT_3B(256‘h0000000000000000000000000000000000000000000000000000000000000000), 334 .INIT_3C(256‘h0000000000000000000000000000000000000000000000000000000000000000), 335 .INIT_3D(256‘h0000000000000000000000000000000000000000000000000000000000000000), 336 .INIT_3E(256‘h0000000000000000000000000000000000000000000000000000000000000000), 337 .INIT_3F(256‘h0000000000000000000000000000000000000000000000000000000000000000), 338 // INIT_A/INIT_B: Initial values on output port 339 .INIT_A(36‘h000000000), 340 .INIT_B(36‘h000000000), 341 // INIT_FILE: Optional file used to specify initial RAM contents 342 .INIT_FILE("NONE"), 343 // RSTTYPE: "SYNC" or "ASYNC" 344 .RSTTYPE("SYNC"), 345 // RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR" 346 .RST_PRIORITY_A("CE"), 347 .RST_PRIORITY_B("CE"), 348 // SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE" 349 .SIM_COLLISION_CHECK("ALL"), 350 // SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior 351 .SIM_DEVICE("SPARTAN3ADSP"), 352 // SRVAL_A/SRVAL_B: Set/Reset value for RAM output 353 .SRVAL_A(36‘h000000000), 354 .SRVAL_B(36‘h000000000), 355 // WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" 356 .WRITE_MODE_A("WRITE_FIRST"), 357 .WRITE_MODE_B("WRITE_FIRST") 358 ) 359 RAMB16BWER_inst ( 360 // Port A Data: 32-bit (each) output: Port A data 361 .DOA(DOA), // 32-bit output: A port data output 362 .DOPA(DOPA), // 4-bit output: A port parity output 363 // Port B Data: 32-bit (each) output: Port B data 364 .DOB(DOB), // 32-bit output: B port data output 365 .DOPB(DOPB), // 4-bit output: B port parity output 366 // Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals 367 .ADDRA(ADDRA), // 14-bit input: A port address input 368 .CLKA(CLKA), // 1-bit input: A port clock input 369 .ENA(ENA), // 1-bit input: A port enable input 370 .REGCEA(REGCEA), // 1-bit input: A port register clock enable input 371 .RSTA(RSTA), // 1-bit input: A port register set/reset input 372 .WEA(WEA), // 4-bit input: Port A byte-wide write enable input 373 // Port A Data: 32-bit (each) input: Port A data 374 .DIA(DIA), // 32-bit input: A port data input 375 .DIPA(DIPA), // 4-bit input: A port parity input 376 // Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals 377 .ADDRB(ADDRB), // 14-bit input: B port address input 378 .CLKB(CLKB), // 1-bit input: B port clock input 379 .ENB(ENB), // 1-bit input: B port enable input 380 .REGCEB(REGCEB), // 1-bit input: B port register clock enable input 381 .RSTB(RSTB), // 1-bit input: B port register set/reset input 382 .WEB(WEB), // 4-bit input: Port B byte-wide write enable input 383 // Port B Data: 32-bit (each) input: Port B data 384 .DIB(DIB), // 32-bit input: B port data input 385 .DIPB(DIPB) // 4-bit input: B port parity input 386 ); 387 388 // End of RAMB16BWER_inst instantiation 389 390 391 // RAMB8BWER : In order to incorporate this function into the design, 392 // Verilog : the following instance declaration needs to be placed 393 // instance : in the body of the design code. The instance name 394 // declaration : (RAMB8BWER_inst) and/or the port declarations within the 395 // code : parenthesis may be changed to properly reference and 396 // : connect this function to the design. All inputs 397 // : and outputs must be connected. 398 399 // <-----Cut code below this line----> 400 401 // RAMB8BWER: 8k-bit Data and 1k-bit Parity Configurable Synchronous Block RAM 402 // Spartan-6 403 // Xilinx HDL Language Template, version 14.7 404 405 RAMB8BWER #( 406 // DATA_WIDTH_A/DATA_WIDTH_B: ‘If RAM_MODE="TDP": 0, 1, 2, 4, 9 or 18; If RAM_MODE="SDP": 36‘ 407 .DATA_WIDTH_A(0), 408 .DATA_WIDTH_B(0), 409 // DOA_REG/DOB_REG: Optional output register (0 or 1) 410 .DOA_REG(0), 411 .DOB_REG(0), 412 // EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST 413 .EN_RSTRAM_A("TRUE"), 414 .EN_RSTRAM_B("TRUE"), 415 // INITP_00 to INITP_03: Initial memory contents. 416 .INITP_00(256‘h0000000000000000000000000000000000000000000000000000000000000000), 417 .INITP_01(256‘h0000000000000000000000000000000000000000000000000000000000000000), 418 .INITP_02(256‘h0000000000000000000000000000000000000000000000000000000000000000), 419 .INITP_03(256‘h0000000000000000000000000000000000000000000000000000000000000000), 420 // INIT_00 to INIT_1F: Initial memory contents. 421 .INIT_00(256‘h0000000000000000000000000000000000000000000000000000000000000000), 422 .INIT_01(256‘h0000000000000000000000000000000000000000000000000000000000000000), 423 .INIT_02(256‘h0000000000000000000000000000000000000000000000000000000000000000), 424 .INIT_03(256‘h0000000000000000000000000000000000000000000000000000000000000000), 425 .INIT_04(256‘h0000000000000000000000000000000000000000000000000000000000000000), 426 .INIT_05(256‘h0000000000000000000000000000000000000000000000000000000000000000), 427 .INIT_06(256‘h0000000000000000000000000000000000000000000000000000000000000000), 428 .INIT_07(256‘h0000000000000000000000000000000000000000000000000000000000000000), 429 .INIT_08(256‘h0000000000000000000000000000000000000000000000000000000000000000), 430 .INIT_09(256‘h0000000000000000000000000000000000000000000000000000000000000000), 431 .INIT_0A(256‘h0000000000000000000000000000000000000000000000000000000000000000), 432 .INIT_0B(256‘h0000000000000000000000000000000000000000000000000000000000000000), 433 .INIT_0C(256‘h0000000000000000000000000000000000000000000000000000000000000000), 434 .INIT_0D(256‘h0000000000000000000000000000000000000000000000000000000000000000), 435 .INIT_0E(256‘h0000000000000000000000000000000000000000000000000000000000000000), 436 .INIT_0F(256‘h0000000000000000000000000000000000000000000000000000000000000000), 437 .INIT_10(256‘h0000000000000000000000000000000000000000000000000000000000000000), 438 .INIT_11(256‘h0000000000000000000000000000000000000000000000000000000000000000), 439 .INIT_12(256‘h0000000000000000000000000000000000000000000000000000000000000000), 440 .INIT_13(256‘h0000000000000000000000000000000000000000000000000000000000000000), 441 .INIT_14(256‘h0000000000000000000000000000000000000000000000000000000000000000), 442 .INIT_15(256‘h0000000000000000000000000000000000000000000000000000000000000000), 443 .INIT_16(256‘h0000000000000000000000000000000000000000000000000000000000000000), 444 .INIT_17(256‘h0000000000000000000000000000000000000000000000000000000000000000), 445 .INIT_18(256‘h0000000000000000000000000000000000000000000000000000000000000000), 446 .INIT_19(256‘h0000000000000000000000000000000000000000000000000000000000000000), 447 .INIT_1A(256‘h0000000000000000000000000000000000000000000000000000000000000000), 448 .INIT_1B(256‘h0000000000000000000000000000000000000000000000000000000000000000), 449 .INIT_1C(256‘h0000000000000000000000000000000000000000000000000000000000000000), 450 .INIT_1D(256‘h0000000000000000000000000000000000000000000000000000000000000000), 451 .INIT_1E(256‘h0000000000000000000000000000000000000000000000000000000000000000), 452 .INIT_1F(256‘h0000000000000000000000000000000000000000000000000000000000000000), 453 // INIT_A/INIT_B: Initial values on output port 454 .INIT_A(18‘h00000), 455 .INIT_B(18‘h00000), 456 // INIT_FILE: Not Supported 457 .INIT_FILE("NONE"), // Do not modify 458 // RAM_MODE: "SDP" or "TDP" 459 .RAM_MODE("TDP"), 460 // RSTTYPE: "SYNC" or "ASYNC" 461 .RSTTYPE("SYNC"), 462 // RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR" 463 .RST_PRIORITY_A("CE"), 464 .RST_PRIORITY_B("CE"), 465 // SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE" 466 .SIM_COLLISION_CHECK("ALL"), 467 // SRVAL_A/SRVAL_B: Set/Reset value for RAM output 468 .SRVAL_A(18‘h00000), 469 .SRVAL_B(18‘h00000), 470 // WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" 471 .WRITE_MODE_A("WRITE_FIRST"), 472 .WRITE_MODE_B("WRITE_FIRST") 473 ) 474 RAMB8BWER_inst ( 475 // Port A Data: 16-bit (each) output: Port A data 476 .DOADO(DOADO), // 16-bit output: A port data/LSB data output 477 .DOPADOP(DOPADOP), // 2-bit output: A port parity/LSB parity output 478 // Port B Data: 16-bit (each) output: Port B data 479 .DOBDO(DOBDO), // 16-bit output: B port data/MSB data output 480 .DOPBDOP(DOPBDOP), // 2-bit output: B port parity/MSB parity output 481 // Port A Address/Control Signals: 13-bit (each) input: Port A address and control signals (write port 482 // when RAM_MODE="SDP") 483 .ADDRAWRADDR(ADDRAWRADDR), // 13-bit input: A port address/Write address input 484 .CLKAWRCLK(CLKAWRCLK), // 1-bit input: A port clock/Write clock input 485 .ENAWREN(ENAWREN), // 1-bit input: A port enable/Write enable input 486 .REGCEA(REGCEA), // 1-bit input: A port register enable input 487 .RSTA(RSTA), // 1-bit input: A port set/reset input 488 .WEAWEL(WEAWEL), // 2-bit input: A port write enable input 489 // Port A Data: 16-bit (each) input: Port A data 490 .DIADI(DIADI), // 16-bit input: A port data/LSB data input 491 .DIPADIP(DIPADIP), // 2-bit input: A port parity/LSB parity input 492 // Port B Address/Control Signals: 13-bit (each) input: Port B address and control signals (read port 493 // when RAM_MODE="SDP") 494 .ADDRBRDADDR(ADDRBRDADDR), // 13-bit input: B port address/Read address input 495 .CLKBRDCLK(CLKBRDCLK), // 1-bit input: B port clock/Read clock input 496 .ENBRDEN(ENBRDEN), // 1-bit input: B port enable/Read enable input 497 .REGCEBREGCE(REGCEBREGCE), // 1-bit input: B port register enable/Register enable input 498 .RSTBRST(RSTBRST), // 1-bit input: B port set/reset input 499 .WEBWEU(WEBWEU), // 2-bit input: B port write enable input 500 // Port B Data: 16-bit (each) input: Port B data 501 .DIBDI(DIBDI), // 16-bit input: B port data/MSB data input 502 .DIPBDIP(DIPBDIP) // 2-bit input: B port parity/MSB parity input 503 ); 504 505 // End of RAMB8BWER_inst instantiation 506 507 508 // RAM256X1S : In order to incorporate this function into the design, 509 // Verilog : the forllowing instance declaration needs to be placed 510 // instance : in the body of the design code. The instance name 511 // declaration : (RAM256X1S_inst) and/or the port declarations within the 512 // code : parenthesis may be changed to properly reference and 513 // : connect this function to the design. All inputs 514 // : and outputs must be connected. 515 516 // <-----Cut code below this line----> 517 518 // RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read 519 // single-port distributed LUT RAM 520 // Spartan-6 521 // Xilinx HDL Language Template, version 14.7 522 523 RAM256X1S #( 524 .INIT(256‘h0000000000000000000000000000000000000000000000000000000000000000) 525 ) RAM256X1S_inst ( 526 .O(O), // Read/write port 1-bit output 527 .A(A), // Read/write port 8-bit address input 528 .WE(WE), // Write enable input 529 .WCLK(WCLK), // Write clock input 530 .D(D) // RAM data input 531 ); 532 533 // End of RAM256X1S_inst instantiation 534 535 536 // RAM64M : In order to incorporate this function into the design, 537 // Verilog : the forllowing instance declaration needs to be placed 538 // instance : in the body of the design code. The instance name 539 // declaration : (RAM64M_inst) and/or the port declarations within the 540 // code : parenthesis may be changed to properly reference and 541 // : connect this function to the design. All inputs 542 // : and outputs must be connected. 543 544 // <-----Cut code below this line----> 545 546 // RAM64M: 64-deep by 4-wide Multi Port LUT RAM 547 // Spartan-6 548 // Xilinx HDL Language Template, version 14.7 549 550 RAM64M #( 551 .INIT_A(64‘h0000000000000000), // Initial contents of A Port 552 .INIT_B(64‘h0000000000000000), // Initial contents of B Port 553 .INIT_C(64‘h0000000000000000), // Initial contents of C Port 554 .INIT_D(64‘h0000000000000000) // Initial contents of D Port 555 ) RAM64M_inst ( 556 .DOA(DOA), // Read port A 1-bit output 557 .DOB(DOB), // Read port B 1-bit output 558 .DOC(DOC), // Read port C 1-bit output 559 .DOD(DOD), // Read/write port D 1-bit output 560 .DIA(DIA), // RAM 1-bit data write input addressed by ADDRD, 561 // read addressed by ADDRA 562 .DIB(DIB), // RAM 1-bit data write input addressed by ADDRD, 563 // read addressed by ADDRB 564 .DIC(DIC), // RAM 1-bit data write input addressed by ADDRD, 565 // read addressed by ADDRC 566 .DID(DID), // RAM 1-bit data write input addressed by ADDRD, 567 // read addressed by ADDRD 568 .ADDRA(ADDRA), // Read port A 6-bit address input 569 .ADDRB(ADDRB), // Read port B 6-bit address input 570 .ADDRC(ADDRC), // Read port C 6-bit address input 571 .ADDRD(ADDRD), // Read/write port D 6-bit address input 572 .WE(WE), // Write enable input 573 .WCLK(WCLK) // Write clock input 574 ); 575 576 // End of RAM64M_inst instantiation 577 578 579 // RAM32X1D : In order to incorporate this function into the design, 580 // Verilog : the forllowing instance declaration needs to be placed 581 // instance : in the body of the design code. The instance name 582 // declaration : (RAM32X1D_inst) and/or the port declarations within the 583 // code : parenthesis may be changed to properly reference and 584 // : connect this function to the design. All inputs 585 // : and outputs must be connected. 586 587 // <-----Cut code below this line----> 588 589 // RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM 590 // Spartan-6 591 // Xilinx HDL Language Template, version 14.7 592 593 RAM32X1D #( 594 .INIT(32‘h00000000) // Initial contents of RAM 595 ) RAM32X1D_inst ( 596 .DPO(DPO), // Read-only 1-bit data output 597 .SPO(SPO), // Rw/ 1-bit data output 598 .A0(A0), // Rw/ address[0] input bit 599 .A1(A1), // Rw/ address[1] input bit 600 .A2(A2), // Rw/ address[2] input bit 601 .A3(A3), // Rw/ address[3] input bit 602 .A4(A4), // Rw/ address[4] input bit 603 .D(D), // Write 1-bit data input 604 .DPRA0(DPRA0), // Read-only address[0] input bit 605 .DPRA1(DPRA1), // Read-only address[1] input bit 606 .DPRA2(DPRA2), // Read-only address[2] input bit 607 .DPRA3(DPRA3), // Read-only address[3] input bit 608 .DPRA4(DPRA4), // Read-only address[4] input bit 609 .WCLK(WCLK), // Write clock input 610 .WE(WE) // Write enable input 611 ); 612 613 // End of RAM32X1D_inst instantiation 614 615 616 // MUXF8 : In order to incorporate this function into the design, 617 // Verilog : the forllowing instance declaration needs to be placed 618 // instance : in the body of the design code. The instance name 619 // declaration : (MUXF8_inst) and/or the port declarations within the 620 // code : parenthesis may be changed to properly reference and 621 // : connect this function to the design. All inputs 622 // : and outputs must be connected. 623 624 // <-----Cut code below this line----> 625 626 // MUXF8: CLB MUX to tie two MUXF7‘s together with general output 627 // Spartan-6 628 // Xilinx HDL Language Template, version 14.7 629 630 MUXF8 MUXF8_inst ( 631 .O(O), // Output of MUX to general routing 632 .I0(I0), // Input (tie to MUXF7 LO out) 633 .I1(I1), // Input (tie to MUXF7 LO out) 634 .S(S) // Input select to MUX 635 ); 636 637 // End of MUXF8_inst instantiation
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原文地址：http://www.cnblogs.com/lyuyangly/p/4852657.html
