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1.状态转移的always中CS，同步ouput的always中NS。
2.3段fsm vs 2段fsm：output逻辑是组合逻辑和同步时序逻辑（消除里不稳的和毛刺）。
3.3段fsm vs 1段fsm: output都是同步时序逻辑，直接根据NS描述output和另外还要考虑状态转移条件描述output。
4.段式划分不是数always个数，而是每种段式对应有固定的描述内容和格式化的结构。强调的是建模思路。
5.3段fsm，解决了2段fsm中不改变时序要求的前提下用寄存器做状态输出的问题。
1 //3-paragraph method to describe FSM 2 //Describe sequential state transition in the 1st sequential always block 3 //State transition conditions in the 2nd combinational always block 4 //Describe the FSM out in the 3rd sequential always block 5 //Westor Wang, Dec. 2006 6 //Verilog Training -- How to write FSM better 7 8 module state3 ( 9 input nrst, 10 input clk, 11 input i1, 12 input i2, 13 output reg o1, 14 output reg o2, 15 output reg err 16 ); 17 18 reg [2:0] NS,CS; 19 20 parameter [2:0] //one hot with zero idle 21 IDLE = 3‘b000, 22 S1 = 3‘b001, 23 S2 = 3‘b010, 24 ERROR = 3‘b100; 25 26 //1st always block, sequential state transition 27 always @ (posedge clk or negedge nrst) 28 if (!nrst) 29 CS <= IDLE; 30 else 31 CS <=NS; 32 33 //2nd always block, combinational condition judgment 34 always @ (nrst or CS or i1 or i2) 35 begin 36 NS = 3‘bx; 37 case (CS) 38 IDLE: begin 39 if (~i1) NS = IDLE; 40 if (i1 && i2) NS = S1; 41 if (i1 && ~i2) NS = ERROR; 42 end 43 S1: begin 44 if (~i2) NS = S1; 45 if (i2 && i1) NS = S2; 46 if (i2 && (~i1)) NS = ERROR; 47 end 48 S2: begin 49 if (i2) NS = S2; 50 if (~i2 && i1) NS = IDLE; 51 if (~i2 && (~i1)) NS = ERROR; 52 end 53 ERROR: begin 54 if (i1) NS = ERROR; 55 if (~i1) NS = IDLE; 56 end 57 endcase 58 end 59 60 61 //3rd always block, the sequential FSM output 62 always @ (posedge clk or negedge nrst) 63 if (!nrst) 64 {o1,o2,err} <= 3‘b000; 65 else 66 begin 67 {o1,o2,err} <= 3‘b000; 68 case (NS) 69 IDLE: {o1,o2,err}<=3‘b000; 70 71 S1: {o1,o2,err}<=3‘b100; 72 S2: {o1,o2,err}<=3‘b010; 73 ERROR: {o1,o2,err}<=3‘b111; 74 endcase 75 end 76 77 endmodule
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原文地址：http://www.cnblogs.com/chip/p/5100459.html
