1.Warning: An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It‘s required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool.
解决办法：是因为timessale不是1ps导致的错误，原因可能是之前使用过modelSim仿真信号时，将timesacle由默认的1ps改成别的值了，可以点击Assignment--->EDA Tool Setting--->Simulation，将选项中的timescale改成1ps，并点击ok进行保存。如果保存时报错，那么将下面的NativeLink setting下的选项选成None，因为这里是testbench测试脚本对应的设置，如果你没有写测试脚本，那么修改timescale时会检查，所以这里将其制定为None就可以了。
2.Nativelink Error
Error: Can‘t launch the ModelSim-Altera software -- the path to the location of the executables for the ModelSim-Altera software were not specified or the executables were not found at specified path.
Error: You can specify the path inthe EDA Tool Options page of the Options dialog box or using the Tcl command set_user_option.
Error: NativeLink simulation flow was NOT successful
解决办法：是因为quartusII不知道你安装的modelSim软件的具体路径，所以需要设置ModelSim的具体路径即可。步骤如下（以ModelSim为例，不是ModelSim Altere）：Tools -> Options -> General -> EDA Tool Options：将选项中的ModelSim设为你安装ModelSim的具体路径即可。如下图：
FPGA quartus开发中常见的错误处理,布布扣,bubuko.com
原文地址：http://www.cnblogs.com/wzd5230/p/3861854.html
