TigerSHARC-101

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芯片特点:

1.数据总线和程序总线分开的哈弗结构

2.采用流水线技术,每条指令都由片内的多个功能单元完成取址译码取数执行等多个步骤.

3.有独立的加法器和乘法器,能够在同一时钟周期完成累加相乘运算.

数字信号处理器(DSP),通用微处理器(MPU),微控制器(MCU)三者的区别在于:DSP 面向高性能,重复性,数值运算密集型的实时处理:MPU 大量用于计算机:MCU 则用于以控制为主的处理过程.

关于定点与浮点.这里有篇博客讲得很清楚.--定点成本低,浮点动态范围大.

KEY FEATURES
    300 MHz, 3.3 ns Instruction Cycle Rate
    6M Bits of Internal—On-Chip—SRAM Memory
    19 mm 19 mm (484-Ball) or 27 mm 27 mm (625-Ball) PBGA Package
    Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, and a Register File
    Dual Integer ALUs, Providing Data Addressing and Pointer Manipulation
    Integrated I/O Includes 14 Channel DMA Controller, External Port, Four Link Ports, SDRAM Controller, Programmable Flag Pins, Two Timers, and Timer
    1149.1 IEEE Compliant JTAG Test Access Port for On-Chip Emulation
    On-Chip Arbitration for Glueless Multiprocessing with up to Eight TigerSHARC Processors on a Bus

TigerSHARC-101

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原文地址：http://www.cnblogs.com/yujone/p/5222850.html