Verilog log2 函数

module simple_dual_ram #(
parameter SIZE  = 10,
  parameter LEN   = 1024
)
(
  input clka,
  input ena,
  input wea,
  input [$clog2(LEN+1)-1 -1:0] addra,//$clog2(8)=3; $clog2(9)=4
  input [SIZE-1:0] dina,
  input clkb, 
  input enb,
  input [$clog2(LEN+1)-1 -1:0] addrb,//
  output reg [SIZE-1:0] doutb
);

function integer funclog2; 
   input integer value; 
   begin 
     value = value-1; 
     for (funclog2=0; value>0; funclog2=funclog2+1) 
       value = value>>1; 
   end 
endfunction 

localparam TEST_LOG2 = funclog2(LEN);
reg [TEST_LOG2-1:0] r_test_log2;

reg [SIZE-1:0] r_data[LEN-1:0];
reg [$clog2(LEN+1)-1:0] r_cnt;//clog2(LEN+1)  clog2(1024+1) -> 11; LOG2(1023+1) -> 10

initial //cannot be synthesis
begin
  doutb <= {(SIZE-1){1‘b0}};
  for(r_cnt=0; r_cnt<LEN; r_cnt=r_cnt+1)
    r_data[r_cnt] <= {(SIZE-1){1‘b0}};
end

always@(posedge clka)
  if(wea&ena)
    r_data[addra] <= dina;

always@(posedge clkb)
  if(enb)
    doutb <= r_data[addrb];


endmodule