标签：fpga verilog
module div_clk(clk_in, divisor, clk_out);
input clk_in;endmodule
TestBench:
module div_tb;
reg clk_in;
wire clk_out;
initial
begin
#0 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
10 clk_in = 1;
#10 clk_in = 0;
10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
end
wire [7 : 0] divisor = 3;
div_clk dc(.clk_in(clk_in),.clk_out(clk_out), .divisor(divisor));
endmodule
[Verilog]任意整数(奇数,整数)分频器设计, 50%占空比,布布扣,bubuko.com
[Verilog]任意整数(奇数,整数)分频器设计, 50%占空比
标签：fpga verilog
原文地址：http://blog.csdn.net/yrj/article/details/38311449
