08-FPGA状态机设计实例——小梅哥FPGA设计思想与验证方法视频教程配套文档

编码格式

状态

二进制

独热码

格雷码

A

3‘b000

8‘b0000_0000

4‘b0000

B

3‘b001

8‘b0000_0010

4‘b0001

C

3‘b010

8‘b0000_0100

4‘b0011

D

3‘b011

8‘b0000_1000

4‘b0010

E

3‘b100

8‘b0001_0000

4‘b0110

F

3‘b101

8‘b0010_0000

4‘b0111

G

3‘b110

8‘b0100_0000

4‘b0101

H

3‘b111

8‘b1000_0000

4‘b0100

module Hello(Clk,Rst_n,data,led);

?

input Clk;//50M

input Rst_n;//低电平复位

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input [7:0]data;

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output reg led;

?

localparam

CHECK_H = 5‘b0_0001,

CHECK_e = 5‘b0_0010,

CHECK_la = 5‘b0_0100,

CHECK_lb = 5‘b0_1000,

CHECK_o = 5‘b1_0000;

?

reg[4:0]state;

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always@(posedge Clk or negedge Rst_n)

if(!Rst_n)begin

led <= 1‘b1;

state <= CHECK_H;

end

else begin

case(state)

CHECK_H:

if(data == "H")

state <= CHECK_e;

else

state <= CHECK_H;

?

CHECK_e:

if(data == "e")

state <= CHECK_la;

else

state <= CHECK_H;

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CHECK_la:

if(data == "l")

state <= CHECK_lb;

else

state <= CHECK_H;

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CHECK_lb:

if(data == "l")

state <= CHECK_o;

else

state <= CHECK_H;

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CHECK_o:

begin

state <= CHECK_H;

if(data == "o")

led <= ~led;

else

led <= led;

end

?

default:state <= CHECK_H;

endcase

end

?

endmodule

`timescale 1ns/1ns

`define clock_period 20

?

module Hello_tb;

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reg Clk;

reg Rst_n;

reg [7:0]ASCII;

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wire led;

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Hello Hello0(

.Clk(Clk),

.Rst_n(Rst_n),

.data(ASCII),

.led(led)

);

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initial Clk = 1;

always#(`clock_period/2)Clk = ~Clk;

?

initial begin

Rst_n = 0;

ASCII = 0;

#(`clock_period*200);

Rst_n = 1;

#(`clock_period*200 + 1);

forever begin

ASCII = "I";

#(`clock_period);

ASCII = "A";

#(`clock_period);

ASCII = "M";

#(`clock_period);

ASCII = "X";

#(`clock_period);

ASCII = "i";

#(`clock_period);

ASCII = "a";

#(`clock_period);

ASCII = "o";

#(`clock_period);

ASCII = "M";

#(`clock_period);

ASCII = "e";

#(`clock_period);

ASCII = "i";

#(`clock_period);

ASCII = "g";

#(`clock_period);

ASCII = "e";

?

#(`clock_period);

ASCII = "H";

#(`clock_period);

ASCII = "E";

?

#(`clock_period);

ASCII = "M";

#(`clock_period);

ASCII = "l";

?

#(`clock_period);

ASCII = "H";

#(`clock_period);

ASCII = "E";

#(`clock_period);

ASCII = "L";

#(`clock_period);

ASCII = "L";

#(`clock_period);

ASCII = "O";

#(`clock_period);

?

ASCII = "H";

#(`clock_period);

ASCII = "e";

#(`clock_period);

ASCII = "l";

#(`clock_period);

ASCII = "l";

#(`clock_period);

ASCII = "o";

?

#(`clock_period);

ASCII = "l";

end

end

?

endmodule