用Vivado写的verilog交通灯课程作业（一）

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2016/05/24 14:55:05
// Design Name: 
// Module Name: traffic
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module traffic(
    input wire clk,
    input wire en,
    input wire rst,
    output reg [2:0] lamp,
    output wire [15:0] seven_seg
    );
    

    
    reg       [7:0]    num        ;
    reg                temp    ;
    reg       [7:0]    red_t    ; 
    reg       [7:0]    yellow_t;
    reg       [7:0]    green_t    ;    
    wire               clkout    ;
    reg       [1:0]    state;
    
    parameter [1:0] red = 2‘d0,
                    
                    green = 2‘d2   ,
                    yellow2 = 2‘d3 ;    
                    

    
    always @ ( posedge clk or negedge rst)
        begin 
            if( rst == 0 )
                begin  
                    state <= 2‘b0 ;    
                    temp  <= 1‘b0 ;    
                    red_t <= 8‘b0010_0101;               //设置灯计时器的预置数，采用BCD码
                    yellow_t <= 8‘b0000_0101;
                    green_t <= 8‘b0010_0000;
                end
            else begin 
                if ( en )     
                    begin
                    if ( !temp ) begin 
                            temp <= 1‘b1;
                            case ( state )              //交通灯状态变换
                                red : begin 
                                    num <= red_t ;
                                    lamp <= 3‘b100;
                                    state <= green;
                                end
                            
                                green : begin 
                                    num <= green_t ;
                                    lamp <= 3‘b001;
                                    state <= yellow2 ;
                                end
                                yellow2 : begin 
                                    num <= yellow_t ;
                                    lamp <= 3‘b010;
                                    state <= red ;
                                end      
                                default : lamp <= 3‘b100 ;
                            endcase
                        end
                    else begin                            //倒计数
                        if ( num >1‘b1 )
                            if ( num [3:0] == 0 ) begin
                                num [ 3:0 ] <= 4‘b1001;
                                num [7:4] <= num [7:4] -1 ;
                            end
                            else num [3:0] <= num [3:0] -1 ;
                            if ( num == 2 )
                                temp <= 0 ;
                        end      
                    end
                else begin 
                    lamp <= 3‘b100 ;
                    state <= red ;
                    temp  <= 0 ;
                end
            end    
      end
     
      
     /************************ 数码管译码**************************************/
    reg        [7:0]    Y_r_1;                
    reg        [7:0]    Y_r_2;
    
    assign seven_seg[7:0] ={1‘b1,(~Y_r_1[6:0])};
    assign seven_seg[15:8] = {1‘b1,(~Y_r_2[6:0])};
    
    always @(num[3:0] )
        begin
            Y_r_1 = 7‘b1111111;
            case (num[3:0] )
                    4‘b0000: Y_r_1 = 7‘b0111111; // 0
                    4‘b0001: Y_r_1 = 7‘b0000110; // 1
                    4‘b0010: Y_r_1 = 7‘b1011011; // 2
                    4‘b0011: Y_r_1 = 7‘b1001111; // 3
                    4‘b0100: Y_r_1 = 7‘b1100110; // 4
                    4‘b0101: Y_r_1 = 7‘b1101101; // 5
                    4‘b0110: Y_r_1 = 7‘b1111101; // 6
                    4‘b0111: Y_r_1 = 7‘b0000111; // 7
                    4‘b1000: Y_r_1 = 7‘b1111111; // 8
                    4‘b1001: Y_r_1 = 7‘b1101111; // 9
                    4‘b1010: Y_r_1 = 7‘b1110111; // A
                    4‘b1011: Y_r_1 = 7‘b1111100; // b
                    4‘b1100: Y_r_1 = 7‘b0111001; // c
                    4‘b1101: Y_r_1 = 7‘b1011110; // d
                    4‘b1110: Y_r_1 = 7‘b1111001; // E
                    4‘b1111: Y_r_1 = 7‘b1110001; // F
                    default: Y_r_1 = 7‘b0000000;
                endcase
        end
    
        always @( num[7:4] )
        begin
            Y_r_2 = 7‘b1111111;
            case ( num[7:4] )
                    4‘b0000: Y_r_2 = 7‘b0111111; // 0
                    4‘b0001: Y_r_2 = 7‘b0000110; // 1
                    4‘b0010: Y_r_2 = 7‘b1011011; // 2
                    4‘b0011: Y_r_2 = 7‘b1001111; // 3
                    4‘b0100: Y_r_2 = 7‘b1100110; // 4
                    4‘b0101: Y_r_2 = 7‘b1101101; // 5
                    4‘b0110: Y_r_2 = 7‘b1111101; // 6
                    4‘b0111: Y_r_2 = 7‘b0000111; // 7
                    4‘b1000: Y_r_2 = 7‘b1111111; // 8
                    4‘b1001: Y_r_2 = 7‘b1101111; // 9
                    4‘b1010: Y_r_2 = 7‘b1110111; // A
                    4‘b1011: Y_r_2 = 7‘b1111100; // b
                    4‘b1100: Y_r_2 = 7‘b0111001; // c
                    4‘b1101: Y_r_2 = 7‘b1011110; // d
                    4‘b1110: Y_r_2 = 7‘b1111001; // E
                    4‘b1111: Y_r_2 = 7‘b1110001; // F
                    default: Y_r_2 = 7‘b0000000;
                endcase
        end 

    
endmodule

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2016/05/24 15:04:09
// Design Name: 
// Module Name: clk_div
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module clk_div(
    input wire rst,
    input wire clk,
    output reg clkout
    );
     
    reg     [31:0]    count1;
    
     always @ ( posedge clk or negedge rst)
        
      begin
        if ( rst== 1‘b0 ) begin
           clkout <= 1‘b0;
           count1 <= 17‘b0; 
        end
      else begin
         if ( count1 >= 32‘d25000000) begin
             clkout <= ~clkout ;
              count1 <=#1  17‘b0; 
              end
            else begin
              count1 <= count1 + 1;
            
            end 
         end 
      end 
endmodule