菜鸟贴；在DE1-S0C上实现了一个FPGA的自动售货机

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存在问题：1，代码很丑！！！2，功能简单

遇到的问题：1，逻辑问题，在一个售货机中也会体现的十分突出。FPGA逻辑和时序是必须关心切着重关心的！！

　　　　　　2，按键和开关存在抖动！但不是逻辑混乱的源头！混乱的源头是逻辑的混乱，过程中出现了无数次逻辑的恼人混乱，其实回想起来大多是由于编写代码是没有很好的考虑时钟和逻辑关系，状态机设计不够熟练，各个状态间的传递关系不清晰！

　　　　　　3，没有经验和做事缺少专注和逻辑：1）对设计过程不应该一口气写到地，应该每写一条代码就清楚它会出现什么现象，没写一个分支就应该考虑清楚它的触发条件，以及他的逻辑和时钟是否会有问题，等等 2）DEGUG是一件痛苦的事情，但一定要注意程序，DEGUG时一定要有耐心和一定的程序，不能凭感觉烂改，重新走一遍代码也是必要的！！！！

以下是详细代码是V1版本

module selfpga(SW,KEY,CLOCK_50,LEDR,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5);
input [9:0] SW;
input [3:0] KEY;
input CLOCK_50;
output [9:0] LEDR;
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5;

reg [9:0] LEDR;
reg [6:0]HEX0,HEX1,HEX2,HEX3,HEX4,HEX5;

reg [7:0] coin_t,coin_o,need;
reg [3:0] state,nextstate;
reg enough,out,ask,can;

parameter idle=4‘b0001;
parameter sel =4‘b0010;
parameter waitin=4‘b0100;
parameter okout=4‘b1000;

always@(posedge CLOCK_50)//状态转换
 begin
  if(KEY[0]) state=nextstate;
  else if(!KEY[0]) state=idle;
  else state=idle;   
 end
always@(state or KEY)//状态逻辑电路
 begin
  //ask=~ask;
  case(state)
   idle:begin
     {LEDR[7],LEDR[8],LEDR[9]}=3‘B001;
    if({SW[2],SW[1],SW[0]}==3‘B0)nextstate=idle;
    else nextstate=sel;
   end
   sel:begin
    {LEDR[7],LEDR[8],LEDR[9]}=3‘B010;
    if({KEY[3],KEY[2],KEY[1]}!=3‘B111)nextstate=waitin;
    else nextstate=sel;
   end
   waitin:begin
   {LEDR[7],LEDR[8],LEDR[9]}=3‘B100;
    if(enough)
     begin
      if(SW[9]) nextstate=okout;
      else if(SW[8]) nextstate=okout;
      else nextstate=waitin;      
     end
    else nextstate=waitin;
   end
   okout:begin
   {LEDR[7],LEDR[8],LEDR[9]}=3‘B111;
    out=1;//找零标志位
    end
   //default:nextstate=idle;
   
  endcase
 end
//-----------------------------------------------

   //end
//__________________________________________________________________________
always@(state or SW)//countneed
begin
  if(state==idle)begin
    need=8‘b0;
    //HEX0=7‘B1111111;
    //HEX1=7‘B1111111;
    //HEX2=7‘B1111111;
    //HEX3=7‘B1111111;
    //HEX4=7‘B0;
    //HEX5=7‘B0;
    LEDR[0]=1‘b1;

    end
  else if(state ==sel)begin
    if({SW[2],SW[1],SW[0]}==3‘b001)
     begin
      need=8‘b00001010;
     end
    else if({SW[2],SW[1],SW[0]}==3‘b010)
     begin
      need=8‘b00011001;
     end
    else if({SW[2],SW[1],SW[0]}==3‘b100)
     begin
      need=8‘b00100011;
     end
    else
     begin
      need=8‘b00000000;
     end
    end
end
always@(posedge CLOCK_50 )//count coin_t
begin
 if(state==waitin)
  begin
    //begin
  if(can==1‘b0)begin
   if(coin_t>=need)begin
    enough=1; LEDR[6]=1‘b1;  LEDR[5]=1‘b0;
   end
   else if(coin_t<need)begin
    LEDR[5]=1‘b1;LEDR[6]=1‘b0;enough=0;
    case({KEY[1],KEY[2],KEY[3]})
    //case({SW[3],SW[4],SW[5]})

    3‘B011: begin    coin_t=coin_t+8‘b00000101;can=1‘b1;end
    3‘B101: begin    coin_t=coin_t+8‘b00001010;can=1‘b1;end
    3‘B110: begin    coin_t=coin_t+8‘b00110010;can=1‘b1;end

    default:begin coin_t=coin_t;can=1‘b0;end
    endcase
   end
  end
  else if(can==1‘b1)
  begin
   if({KEY[1],KEY[2],KEY[3]}==3‘B111)can=1‘b0;
   //if({SW[3],SW[4],SW[5]}==3‘b111)can=1‘b0;
  end 
    
 end
 else if(state==idle)begin
    coin_t=8‘b0;
    //coin_o=8‘b0;
    enough=1‘b0;
    can=1‘b0;
    LEDR[5]=1‘B0;
    LEDR[6]=1‘B0;end
 else if (state ==sel);
 else ;
end
always@(state)//count coin_O
begin
 if(state==okout)
  begin
   if(SW[9])begin
   coin_o=coin_t - need;
   end
   else if(SW[8])begin
   coin_o=coin_t;
   end
   
  end
 else if (state==idle)begin coin_o=8‘b0;end
end

 always@(need)//display
 begin

   begin
    if({SW[2],SW[1],SW[0]}==3‘b001)
     begin
      HEX0=7‘b1000000;
      HEX1=7‘b1111001;
     end
    else if({SW[2],SW[1],SW[0]}==3‘b010)
     begin
      HEX1=7‘b0100100;
      HEX0=7‘b0010010;
     end
    else if({SW[2],SW[1],SW[0]}==3‘b100)
     begin
      HEX1=7‘b0110000;
      HEX0=7‘b0010010;
     end
    else
     begin
      HEX0=7‘B1000000;
      HEX1=7‘b1000000;
     end
   end
 end
 always@(coin_t)//display
 begin
   case(coin_t)
             /*
          hex
          0 7‘b1000000          1 7‘b1111001          2 7‘b0100100
          3 7‘b0110000          4 7‘b0011001          5 7‘b0010010
          6 7‘b0000010          7 7‘b1111000          8 7‘b0000000
          9 7‘b0010000
              */  8‘b00000000:begin HEX3=7‘B1000000;HEX2=7‘B1000000;end
     
      8‘b00000101:begin HEX3=7‘b1000000;HEX2=7‘b0010010;end//5      
      8‘b00001010:begin HEX3=7‘b1111001;HEX2=7‘b1000000;end//10
      8‘b00001111:begin HEX3=7‘b1111001;HEX2=7‘b0010010;end//15
      
      8‘b00010100:begin HEX3=7‘b0100100;HEX2=7‘b1000000;end//20
      8‘b00011001:begin HEX3=7‘b0100100;HEX2=7‘b0010010;end//25
      
      8‘b00011110:begin HEX3=7‘b0110000;HEX2=7‘b1000000;end//30
      8‘b00100011:begin HEX3=7‘b0110000;HEX2=7‘b0010010;end//35
      
      8‘b00101000:begin HEX3=7‘b0011001;HEX2=7‘b1000000;end//40
      8‘b00101101:begin HEX3=7‘b0011001;HEX2=7‘b0010010;end//45
      
      8‘b00110010:begin HEX3=7‘b0010010;HEX2=7‘b1000000;end//50
      8‘b00110111:begin HEX3=7‘b0010010;HEX2=7‘b0010010;end//55
      
      8‘b00111100:begin HEX3=7‘b0000010;HEX2=7‘b1000000;end//60
      8‘b01000001:begin HEX3=7‘b0000010;HEX2=7‘b0010010;end//65
      
      8‘b01000110:begin HEX3=7‘b1111000;HEX2=7‘b1000000;end//70
      8‘b01001011:begin HEX3=7‘b1111000;HEX2=7‘b0010010;end//75
      
      8‘b01010000:begin HEX3=7‘b0000000;HEX2=7‘b1000000;end//80
      default: begin
       HEX2=7‘Bx;
       HEX3=7‘Bx;
      end
    
    endcase
//____________________________________________________________________________

  // sel:
     
//***************************************************************************

    //end

   //end
   

   //111111111111

//**************************************************************************88
  /* okout:begin
    if(SW[9])begin
     coin_o=coin_t-need;
     case(coin_o)
      7‘b0000101:;
      7‘b0001010:;
      7‘b0110010:;
     endcase
    end
    else if(SW[8])begin
     coin_o=coin_t;
     case(coin_o)
      7‘b0000101:;
      7‘b0001010:;
      7‘b0110010:;      
     endcase 
    end
   end
  endcase*/
 end

always@(coin_o)
begin
if (state ==idle)begin HEX5=7‘B1000000;HEX4=7‘B1000000;end
else
  case(coin_o)
    
               8‘b00000000:begin HEX5=7‘B1000000;HEX4=7‘B1000000;end
     
      8‘b00000101:begin HEX5=7‘b1000000;HEX4=7‘b0010010;end//5      
      8‘b00001010:begin HEX5=7‘b1111001;HEX4=7‘b1000000;end//10
      8‘b00001111:begin HEX5=7‘b1111001;HEX4=7‘b0010010;end//15
      
      8‘b00010100:begin HEX5=7‘b0100100;HEX4=7‘b1000000;end//20
      8‘b00011001:begin HEX5=7‘b0100100;HEX4=7‘b0010010;end//25
      
      8‘b00011110:begin HEX5=7‘b0110000;HEX4=7‘b1000000;end//30
      8‘b00100011:begin HEX5=7‘b0110000;HEX4=7‘b0010010;end//35
      
      8‘b00101000:begin HEX5=7‘b0011001;HEX4=7‘b1000000;end//40
      8‘b00101101:begin HEX5=7‘b0011001;HEX4=7‘b0010010;end//45
      
      8‘b00110010:begin HEX5=7‘b0010010;HEX4=7‘b1000000;end//50
      8‘b00110111:begin HEX5=7‘b0010010;HEX4=7‘b0010010;end//55
      
      8‘b00111100:begin HEX5=7‘b0000010;HEX4=7‘b1000000;end//60
      8‘b01000001:begin HEX5=7‘b0000010;HEX4=7‘b0010010;end//65
      
      8‘b01000110:begin HEX5=7‘b1111000;HEX4=7‘b1000000;end//70
      8‘b01001011:begin HEX5=7‘b1111000;HEX4=7‘b0010010;end//75
      
      8‘b01010000:begin HEX5=7‘b0000000;HEX4=7‘b1000000;end//80
      default: begin
       HEX4=7‘B1000000;
       HEX5=7‘B1000000;
      end
    
    endcase
    
end

endmodule

菜鸟贴；在DE1-S0C上实现了一个FPGA的自动售货机

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原文地址：http://www.cnblogs.com/threethousandhours/p/5559868.html