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原文地址：http://www.fpga4fun.com/PCI-Express.html
前言：
As PCI Express becomes common place in high-end FPGAs, let‘s see how easy FPGA vendors made the technology available.
In particular, we look more closely at Xilinx‘s PCI Express solution.
全文分为六个部分，第一部分：
PCI Express comes commonly in two sizes: 1-lane and 16-lanes, with 1-lane used for regular boards and 16-lanes used for graphic cards.
The 1-lane connector has 36 contacts, arranged in two rows of 18 contacts.
Here‘s a top view.
Of the 36 contacts, only 6 are useful to the transport of data, the rest are power pins and other auxiliary signals. The 6 functional contacts are used in 3 pairs:
The pairs are often referred as "differential pairs" because each signal from a pair carries the same signal but with one inverted from the other. The reason for using differential pairs is mainly reliability of transmission and will be discussed in more details later.
In PCI Express generation 1 (or simply "Gen1"), the PET and PER pairs have data transmitted at a speed of 2.5Gbps. Gen2 doubles that.
Looking at the Dragon-E board, we can recognize the PET pair below the FPGA.
To work correctly, the lines in a differential pair need to be electrically coupled and have no impedance discontinuities, which in practice means something like "stay close together" and "no sharp angles". That‘s the reason for the Dragon-E‘s PET pair serpentine shape. The other side of the board shows the two other serpentine pairs REFCLK and PER.
To allows for more speed, multiple lanes can be used. The REFCLK pair doesn‘t need to be duplicated, so for example, PCI Express with 2 lanes uses 5 pairs (1 REFCLK + 2 PET + 2 PER).
Graphic boards often use 16 lanes connectors in what is commonly called PCI Express x16.
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原文地址：http://www.cnblogs.com/christsong/p/5720507.html
