标签:
Language |
Support |
VHDL |
IEEE-STD-1076-2000 |
Verilog |
IEEE-STD-1364-2001 |
SDF |
Xilinx’s NetGen generated SDF Files |
VITAL |
VITAL-2000 |
Mixed VHDL/Verilog |
Yes |
VHDL FLI/VHPI |
No |
Verilog PLI |
No |
System Verilog |
No |
Feature |
Support |
Incremental Compilation |
Yes |
Source Code Debugging |
Yes |
SDF Annotation |
Yes |
VCD Generation |
Yes |
Hard IP - MGT, PPC, PCIE, etc |
Yes |
Shortcut Key |
Function |
F5 |
Refresh |
F6 |
Zoom Full View |
F7 |
Zoom Out |
F8 |
Zoom In |
F9 |
Zoom to Box |
Ctrl+Shift+Left Mouse Button |
Mouse Drag Zoom |
Key Sequence |
Test Bench Waveform Menu Command |
Alt+T, E |
Set End of Test Bench |
Alt+T, R |
Rescale Timing |
Alt+T, S |
Set "Result File" Name |
Alt+T, V |
Goto Previous Transition |
Alt+T, X |
Goto Next Transition |
Alt+T, I |
Goto Time |
Alt+T, G |
Goto Marker menu |
Alt+T, F |
Find Signal |
Alt+T, M |
Marker Menu |
Alt+T, Z |
Zoom Menu |
Alt+T, C |
Close Windows |
Key Sequence |
Simulation Menu Command |
Alt+U, R |
Restart |
Alt+U, S |
Stop |
Alt+U, T |
Step |
Alt+U, A |
Run All |
Alt+U, U |
Run For Specified Time |
Alt+U, V |
Goto Previous Transition |
Alt+U, X |
Goto Next Transition |
Alt+U, I |
Goto Time |
Alt+U, G |
Goto Marker menu |
Alt+U, F |
Find Signal |
Alt+U, M |
Marker Menu |
Alt+U, Z |
Zoom Menu |
Alt+U, E |
End Simulation |
ISim可以实现GUI/命令行形式的行为级仿真,其仿真流程如下框图所示
可在不使用HDL或其它脚本语言的情况下,利用TBW指定测试激励的值和长度。同时可以随时利用命令View Generated Test Bench as HDL process将波形激励转化成HDL语言形式。在窗口可进行端口的重命名、添加和删除等操作。
创建波形仿真文件/HDL仿真文件/加载已有文件->利用菜单/快捷键/tcl命令运行仿真(可设置断点);使用DO文件仿真->步进仿真->停止仿真->保存仿真结果
由于命令的种类多,参数和使用复杂,这里从略。。。
文档程序:Xilinx ISE Help/Software Help/ISE Simulator (ISim) Help
标签:
原文地址:http://www.cnblogs.com/leyou2016/p/ISim.html