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Verilog HDL Test Bench

时间:2016-09-22 01:05:17      阅读:258      评论:0      收藏:0      [点我收藏+]

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As digital systems becomes more complex,it becomes increasingly important to verify the functionality of a design before implementing it in a system,a Test Bench source includes mainly some aspects:

0,set up time scale and operating precision.

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1,instantiation

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2,Reg and Wire Declarations

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3,initial and always(clock,reset)

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waring:

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4,Printing during simulusation

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5,TASK

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Verilog HDL Test Bench

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原文地址:http://www.cnblogs.com/rrttp/p/5894694.html

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