Verilog学习笔记简单功能实现（六）...............计数分频电路

 1 module half_clk(clr,clk_in,clk_out,out2);
 2   input clr,clk_in;
 3   output clk_out,out2; 
 4   reg clk_out,out2;
 5   
 6   always @(posedge clk_in)
 7   begin
 8   if (clr==0) begin clk_out=0; out2=1;end
 9     else begin clk_out<=~clk_out; out2=~out2;end
10   end
11 endmodule 

 1 module fdivision(rst,clkin,clkout);
 2   input rst,clkin;
 3   output clkout;
 4   reg clkout;
 5   reg [4:0]i;
 6   always @(posedge clkin)
 7   begin
 8   if(!rst) begin clkout<=0; i<=0;end
 9     else begin
10          if(i==19)
11            begin clkout<=~clkout;i<=0;end
12            else
13           i<=i+1;
14          end
15   end
16 endmodule 

 1 module fdivision5(clkin,clkout);
 2   input  clkin;
 3   output clkout;
 4   wire clkout;
 5   reg [2:0]step,step1;
 6   always @(posedge clkin)
 7   begin
 8     case(step)
 9       3‘b000:step<=3‘b010;
10       3‘b010:step<=3‘b100;
11       3‘b100:step<=3‘b001;
12       3‘b001:step<=3‘b011;
13       3‘b011:step<=3‘b000;
14       default step<=3‘b000;
15     endcase
16   end
17   always @(negedge clkin)
18   begin
19   case(step1)
20       3‘b000:step1<=3‘b010;
21       3‘b010:step1<=3‘b100;
22       3‘b100:step1<=3‘b001;
23       3‘b001:step1<=3‘b011;
24       3‘b011:step1<=3‘b000;
25       default step1<=3‘b000;
26     endcase
27   end
28   assign clkout=(step[0]|step1[0]);
29 endmodule

 1 `timescale 1ns/1ns
 2 `define half_period 20
 3 module fdivision5_test;
 4   reg  clkin;
 5   wire clkout;
 6   wire step,step1;
 7   initial
 8   begin
 9   clkin=0;
10   end
11   always #`half_period clkin=~clkin;
12   fdivision5 m(clkin,clkout);
13   assign step=m.step;
14   assign step1=m.step1;
15 endmodule