Wishbone总线从接口转Xilinx MIG (Spartan 6)

  1 //***************************************************************************
  2 //   Copyright(c)2016, Lyu Yang
  3 //   All rights reserved
  4 //
  5 //   File name        :   wb_xmigddr.v
  6 //   Module name      :   
  7 //   Author           :   Lyu Yang
  8 //   Email            :   lyuyangly@qq.com
  9 //   Date             :   2016-12-00
 10 //   Version          :   v1.0
 11 //
 12 //   Abstract         :   DDR Chip Clock Source is 50MHz.
 13 //
 14 //   Modification history
 15 //   ------------------------------------------------------------------------
 16 // Version       Data(yyyy/mm/dd)   name
 17 // Description
 18 //
 19 // $Log$
 20 //***************************************************************************
 21 `timescale 1ns / 100ps
 22 module wb_xmigddr (
 23     input                                           wb_clk_i,
 24     input                                           wb_rst_i,
 25 
 26     // Wishbone Interface
 27     input                                           wb_cyc_i,
 28     input                                           wb_stb_i,
 29     input                                           wb_we_i,
 30     input [3:0]                                     wb_sel_i,
 31     input [31:0]                                    wb_adr_i,
 32     input [31:0]                                    wb_dat_i,
 33     output [31:0]                                   wb_dat_o,
 34     output                                            wb_ack_o,
 35     
 36     // DDR Chip Signals
 37     output                                            mcb3_dram_ck,
 38     output                                            mcb3_dram_ck_n,
 39     inout  [15:0]                                    mcb3_dram_dq,
 40     output [12:0]                                    mcb3_dram_a,
 41     output [2:0]                                    mcb3_dram_ba,
 42     output                                            mcb3_dram_ras_n,
 43     output                                            mcb3_dram_cas_n,
 44     output                                            mcb3_dram_we_n,
 45     output                                            mcb3_dram_odt,
 46     output                                            mcb3_dram_cke,
 47     output                                            mcb3_dram_dm,
 48     inout                                            mcb3_dram_udqs,
 49     inout                                            mcb3_dram_udqs_n,
 50     output                                            mcb3_dram_udm,
 51     inout                                            mcb3_dram_dqs,
 52     inout                                            mcb3_dram_dqs_n,
 53     inout                                            mcb3_rzq,
 54     inout                                            mcb3_zio
 55 );
 56 
 57 // DDR DRAM Calib Done
 58 wire                c3_calib_done;
 59 // BIU Signals
 60 wire                c3_px_cmd_en;
 61 wire    [2:0]        c3_px_cmd_instr;
 62 wire    [29:0]        c3_px_cmd_byte_addr;
 63 wire                c3_px_cmd_full;
 64 wire                c3_px_wr_en;
 65 wire                c3_px_wr_empty;
 66 wire                c3_px_rd_en;
 67 wire                c3_px_rd_empty;
 68 
 69 
 70 // Read, Write and Ack Signals
 71 wire                wb_req;
 72 reg                    wb_req_r, wb_ack_write, wb_ack_read;
 73 
 74 assign wb_req = wb_stb_i & wb_cyc_i & c3_calib_done; 
 75 
 76 always @(posedge wb_clk_i)
 77     wb_req_r <= wb_req & !wb_ack_o;
 78 
 79 assign wb_req_new  = wb_req & !wb_req_r;
 80 
 81 // Write and Read Ack Signal
 82 always @(posedge wb_clk_i)
 83     wb_ack_write <= wb_req & wb_we_i & !wb_ack_write & !c3_px_cmd_full;
 84 
 85 always @(posedge wb_clk_i)
 86     wb_ack_read <= wb_req & !wb_we_i & !wb_ack_read & !c3_px_rd_empty;
 87 
 88 
 89 assign wb_ack_o = (wb_we_i ? wb_ack_write : wb_ack_read) & wb_stb_i;
 90 assign c3_px_cmd_instr = {2‘b00, ~wb_we_i};
 91 assign c3_px_cmd_byte_addr = {wb_adr_i[29:2], 2‘b00};
 92 assign c3_px_wr_en = (wb_stb_i & wb_cyc_i & wb_we_i) ? wb_req_new : 1‘b0;
 93 assign c3_px_rd_en = (wb_stb_i & wb_cyc_i & !wb_we_i) ? wb_ack_read : 1‘b0;
 94 assign c3_px_cmd_en = (wb_stb_i & wb_cyc_i & wb_we_i) ? wb_ack_write : wb_req_new & !wb_we_i;
 95 
 96 
 97 // Xilinx Spartan6 MIG
 98 mig_spartan6 memc_ddr
 99 (
100     // controller clock and reset
101     .c3_sys_clk                    (wb_clk_i),
102     .c3_sys_rst_i                (wb_rst_i),
103     
104     // user insterface signals
105     .c3_p0_cmd_clk                (wb_clk_i),
106     .c3_p0_cmd_en                (c3_px_cmd_en),
107     .c3_p0_cmd_instr            (c3_px_cmd_instr),
108     .c3_p0_cmd_bl                (‘d0),
109     .c3_p0_cmd_byte_addr        (c3_px_cmd_byte_addr),
110     .c3_p0_cmd_empty            (),
111     .c3_p0_cmd_full                (c3_px_cmd_full),
112     .c3_p0_wr_clk                (wb_clk_i),
113     .c3_p0_wr_en                (c3_px_wr_en),
114     .c3_p0_wr_mask                (~wb_sel_i),
115     .c3_p0_wr_data                (wb_dat_i),
116     .c3_p0_wr_full                (),
117     .c3_p0_wr_empty                (c3_px_wr_empty),
118     .c3_p0_wr_count                (),
119     .c3_p0_wr_underrun            (),
120     .c3_p0_wr_error                (),
121     .c3_p0_rd_clk                (wb_clk_i),
122     .c3_p0_rd_en                (c3_px_rd_en),
123     .c3_p0_rd_data                (wb_dat_o),
124     .c3_p0_rd_full                (),
125     .c3_p0_rd_empty                (c3_px_rd_empty),
126     .c3_p0_rd_count                (),
127     .c3_p0_rd_overflow            (),
128     .c3_p0_rd_error                (),
129     // port1
130     .c3_p1_cmd_clk                (),
131     .c3_p1_cmd_en                (1‘b0),
132     .c3_p1_cmd_instr            (),
133     .c3_p1_cmd_bl                (),
134     .c3_p1_cmd_byte_addr        (),
135     .c3_p1_cmd_empty            (),
136     .c3_p1_cmd_full                (),
137     .c3_p1_wr_clk                (),
138     .c3_p1_wr_en                (1‘b0),
139     .c3_p1_wr_mask                (),
140     .c3_p1_wr_data                (),
141     .c3_p1_wr_full                (),
142     .c3_p1_wr_empty                (),
143     .c3_p1_wr_count                (),
144     .c3_p1_wr_underrun            (),
145     .c3_p1_wr_error                (),
146     .c3_p1_rd_clk                (),
147     .c3_p1_rd_en                (1‘b0),
148     .c3_p1_rd_data                (),
149     .c3_p1_rd_full                (),
150     .c3_p1_rd_empty                (),
151     .c3_p1_rd_count                (),
152     .c3_p1_rd_overflow            (),
153     .c3_p1_rd_error                (),
154     // port2
155     .c3_p2_cmd_clk                (),
156     .c3_p2_cmd_en                (1‘b0),
157     .c3_p2_cmd_instr            (),
158     .c3_p2_cmd_bl                (),
159     .c3_p2_cmd_byte_addr        (),
160     .c3_p2_cmd_empty            (),
161     .c3_p2_cmd_full                (),
162     .c3_p2_wr_clk                (),
163     .c3_p2_wr_en                (1‘b0),
164     .c3_p2_wr_mask                (),
165     .c3_p2_wr_data                (),
166     .c3_p2_wr_full                (),
167     .c3_p2_wr_empty                (),
168     .c3_p2_wr_count                (),
169     .c3_p2_wr_underrun            (),
170     .c3_p2_wr_error                (),
171     .c3_p2_rd_clk                (),
172     .c3_p2_rd_en                (1‘b0),
173     .c3_p2_rd_data                (),
174     .c3_p2_rd_full                (),
175     .c3_p2_rd_empty                (),
176     .c3_p2_rd_count                (),
177     .c3_p2_rd_overflow            (),
178     .c3_p2_rd_error                (),
179     // port3
180     .c3_p3_cmd_clk                (),
181     .c3_p3_cmd_en                (1‘b0),
182     .c3_p3_cmd_instr            (),
183     .c3_p3_cmd_bl                (),
184     .c3_p3_cmd_byte_addr        (),
185     .c3_p3_cmd_empty            (),
186     .c3_p3_cmd_full                (),
187     .c3_p3_wr_clk                (),
188     .c3_p3_wr_en                (1‘b0),
189     .c3_p3_wr_mask                (),
190     .c3_p3_wr_data                (),
191     .c3_p3_wr_full                (),
192     .c3_p3_wr_empty                (),
193     .c3_p3_wr_count                (),
194     .c3_p3_wr_underrun            (),
195     .c3_p3_wr_error                (),
196     .c3_p3_rd_clk                (),
197     .c3_p3_rd_en                (1‘b0),
198     .c3_p3_rd_data                (),
199     .c3_p3_rd_full                (),
200     .c3_p3_rd_empty                (),
201     .c3_p3_rd_count                (),
202     .c3_p3_rd_overflow            (),
203     .c3_p3_rd_error                (),
204    
205     // ddr2 chip signals
206     .mcb3_dram_dq                (mcb3_dram_dq),
207     .mcb3_dram_a                (mcb3_dram_a),
208     .mcb3_dram_ba                (mcb3_dram_ba),
209     .mcb3_dram_ras_n            (mcb3_dram_ras_n),
210     .mcb3_dram_cas_n            (mcb3_dram_cas_n),
211     .mcb3_dram_we_n                (mcb3_dram_we_n),
212     .mcb3_dram_odt                (mcb3_dram_odt),
213     .mcb3_dram_cke                (mcb3_dram_cke),
214     .mcb3_dram_dm                (mcb3_dram_dm),
215     .mcb3_dram_udqs                (mcb3_dram_udqs),
216     .mcb3_dram_udqs_n            (mcb3_dram_udqs_n),
217     .mcb3_dram_udm                (mcb3_dram_udm),
218     .mcb3_dram_dqs                (mcb3_dram_dqs),
219     .mcb3_dram_dqs_n            (mcb3_dram_dqs_n),
220     .mcb3_dram_ck                (mcb3_dram_ck),
221     .mcb3_dram_ck_n                (mcb3_dram_ck_n),
222     .mcb3_rzq                    (mcb3_rzq),
223     .mcb3_zio                    (mcb3_zio),
224     .c3_clk0                    (),
225     .c3_rst0                    (),
226     .c3_calib_done                (c3_calib_done)
227 );
228 
229 
230 endmodule