简易数据加密传输电路（VHDL）（原创）

 1 LIBRARY IEEE;
 2 USE IEEE.STD_LOGIC_1164.ALL;
 3 USE IEEE.std_logic_unsigned.ALL;
 4 
 5 ENTITY KEKE IS  --定义实体wsj1
 6     GENERIC(n : positive := 16);
 7     
 8     PORT(CLK:IN STD_LOGIC;--时钟信号
 9         CTL:IN STD_LOGIC;--控制信号      
10         V1:BUFFER STD_LOGIC;--假设伪随机序列1作为待价密数据
11          V2:BUFFER STD_LOGIC;--伪随机序列二作为密钥数据流v2
12           V3:BUFFER STD_LOGIC;--V3为异或后生成的加密数据串行输出
13           V4:BUFFER STD_LOGIC;--解密数据流应该和密钥数据流v2相同
14           V5:BUFFER STD_LOGIC--v3和v4异或解密得到结果v5
15         ); 
16 END KEKE;
17 
18 ARCHITECTURE BEHAV OF KEKE IS
19 
20 SIGNAL C0,C1,C2,C3,C4,C5,C6,C7:STD_LOGIC;--伪随机序列1作为待价密数据
21 SIGNAL A0,A1,A2,A3,A4,A5,A6,A7:STD_LOGIC;--伪随机序列二作为密钥数据流v2 和解密数据流v4
22 
23 BEGIN
24   ----伪随机序列1作为待价密数据
25     PROCESS(CLK, CTL) 
26         BEGIN
27             IF CLK‘EVENT AND CLK=‘1‘ THEN
28                 IF ( CTL=‘1‘) THEN
29                     C7<=‘0‘;C6<=‘0‘;C5<=‘0‘;C4<=‘0‘;C3<=‘0‘;C2<=‘0‘;C1<=‘0‘;C0<=‘1‘;V1<=C7;
30                 ELSE
31                     C1<=C0;C2<=C1; C3<=C2;C4<=C3;C5<=C4;C6<=C5;C7<=C6;
32                     C0<=C7 XOR C4 XOR C3 XOR C2  ;  
33                     V1<=C7;
34                 END IF;
35             END IF;    
36     END PROCESS;
37     ----伪随机序列二作为密钥数据流v2 和解密数据流v4
38     PROCESS(CLK, CTL)     --设置敏感量
39         BEGIN
40             IF CLK‘EVENT AND CLK=‘1‘ THEN
41                 IF ( CTL=‘1‘) THEN
42                     A7<=‘0‘;A6<=‘0‘;A5<=‘0‘;A4<=‘0‘;A3<=‘0‘;A2<=‘0‘;A1<=‘0‘;A0<=‘1‘;V2<=A7;V4<=A7;
43                 ELSE
44                     A1<=A0;A2<=A1; A3<=A2;A4<=A3;A5<=A4;A6<=A5;A7<=A6;
45                     A0<=A7 XOR A1; 
46                     V2<=A7;
47                    V4<=A7;
48                 END IF;
49             END IF;    
50     END PROCESS;
51     ----v3密文数据为v1v2异或得到
52    V3<=V1 xor V2;    
53     ----v5密文数据为v3v4异或得到明文数据应该和v1一样
54     V5<=V3 xor V4;
55 END BEHAV;