标签:end map proc class gui 批处理 module turn return
名称 | 描述 |
get_code.tcl | 自动搜索自动目录下的verilog文件,并编译 |
sim.do | 设置顶层文件,通过vsim命令,启动仿真 |
sim.bat | 批处理文件,新建运行目录,并执行get_code.tcl和sim.do文件 |
set code_file "vlog.f" file delete -force "$code_file" ### 源代码搜索子程序 proc file_search {file_dir file_name} { set path_list "" if {[glob -directory $file_dir -nocomplain -- $file_name] != ""} { append path_list [glob -directory $file_dir -nocomplain -- $file_name]\n; } foreach sub_dir [lsort -dictionary [glob -directory $file_dir -type d -nocomplain *]] { append path_list [file_search $sub_dir $file_name]; } return $path_list; } ### 搜索.v 文件 proc gen_vlg_list {output_list directory_filter} { set file_list [file_search $directory_filter *.\[vV\]] set code_list [open [file join [pwd] $output_list] a] foreach file_list_all $file_list { puts $code_list "$file_list_all" } close $code_list } ### 搜索.vo程序 proc gen_vo_list {output_list directory_filter} { set file_list [file_search $directory_filter *.vo] set code_list [open [file join [pwd] $output_list] a] foreach file_list_all $file_list { puts $code_list "$file_list_all" } close $code_list } ### 搜索.vhd程序 proc gen_vhd_list {output_list directory_filter} { set file_list [file_search $directory_filter *.vhd] set code_list [open [file join [pwd] $output_list] a] foreach file_list_all $file_list { #puts $code_list "$file_list_all" vcom -work work "$file_list_all" } close $code_list } ### #### 添加 `include 搜索路径 ############## ################################################################### # compile ################################################################### if {[file exists work] == 0} { exec vlib work exec vmap work work } set incdir_list [open $code_file a] puts $incdir_list [format "+incdir+../tb"] close $incdir_list gen_vlg_list $code_file ../tb gen_vlg_list $code_file ../../src gen_vlg_list $code_file ../../ipcore_dir #gen_vhd_list $code_file ../../ipcore_dir/example_design/ if { [file exists compile_error] == 1 } { file delete -force compile_error } if {[catch {exec vlog -incr -sv -novopt -work work -f $code_file > compile.log} err_info]} { set err_flag [open compile_error a] puts $err_flag [format "compile error" ] exec notepad [file nativename compile.log] exit }
sim.do
#set tb_module cnt_tb set path [pwd] set proj_dir [file dirname $path] set tbfile [glob -nocomplain [file join [file join $proj_dir "tb" ] "*_tb.v"]] regsub {.*/(\w+)\.v} $tbfile {\1} tb_module # puts "Top level is $tb_module" quit -sim #### vsim startup # vsim -l vsim.log -quiet -novopt -t ns +notimingcheck -L XilinxCoreLib_ver -L unisims_ver glbl -L work $tb_module onerror {resume} radix hex if { [file exists wave.do] } { do wave.do } else { add wave /$tb_module/* } #run -all
sim.bat
@echo off
:: testcase
set TC=%1
:: gui or not: -c = not gui; [empty] = gui
set vsim_c=%2
md %TC%
CD %TC%
:: 复制mcu rom code
::copy ..\..\integration_kit\validation\tests\%TC%.bin image.bin
::pause
:: 获取文件列表 并编译
tclsh85 ..\get_code.tcl
:: 启动modelsim仿真
if not exist compile_error vsim -do ..\sim.do %vsim_c%
if not exist compile_error start vsim.log
cd ../
标签:end map proc class gui 批处理 module turn return
原文地址:http://www.cnblogs.com/xinlukk/p/6978661.html