标签：data ext rcc byte manual mode blank poi control
转载请注明原文出处，http://www.cnblogs.com/flyingcloude/p/6992339.html
PROGRAM start
RSEG ICODE:DATA(2) ;RSEG定义段, 其中ICODE等名称需要与XCL文件中的名称对应。DATA是类型
RSEG CODE:DATA(2)
RSEG INITTAB:DATA(2)
RSEG DATA_C:DATA(2)
RSEG DATA_ID:DATA(2)
RSEG DATA_I:DATA(2)
RSEG DATA_Z:DATA(2)
RSEG ICODE:CODE:ROOT(2)
INCLUDE ebi.inc
INCLUDE Config.inc
INCLUDE isr.macro
ORG 0x0
CODE32
PUBLIC __program_start
IMPORT main
;__program_start 程序入口
__program_start
b ?ResetHandler
b ?UndefHandler
b ?SWIHandler
b ?PrefetchAbortHandler
b ?DataAbortHandler
b . ; Reserved
TestBit ;用来测试是通过RAM或FLASH启动
DCD 0 ;for boot test
?UndefHandler b ?UndefHandler
?SWIHandler b ?SWIHandler
?PrefetchAbortHandler b ?PrefetchAbortHandler
?DataAbortHandler b ?DataAbortHandler
?ResetHandler ;初始化AIC，禁止中断
ldr r1,=AIC_BASE ;AIC_BASE = 0xfffff000
ldr r0,=0xffffffff
str r0,[r1,#AIC_IDCR]
?EBI_Init ;初始化EBI
ldr r11, =EBI_Config
ldmia r11!, {r0-r10}
stmia r10!, {r0-r9} ;ebi init,not remap yet
ldr r0,=0x0a0a0a0a ;boot test--flash or ram?
ldr r1,=TestBit
str r0,[r1]
ldr r1,[r1]
cmp r0,r1
ldreq r8,=0
beq ?DATA_I_Init ;ram boot
ldrne r8,=1
bne ?RO_RW_Init ;flash boot
?RO_RW_Init
;before remap
ldr r0,=SFB(ICODE)
add r0,r0,#0x300000 ;on-chip ram base addr is 0x300000 before remap
ldr r1,=SFE(DATA_C)
add r1,r1,#0x300000
ldr r2,=0 ;flash base addr before remap
La1 ;copy ro+rw from flash to ram
cmp r0, r1
ldrcc r3, [r2], #4
strcc r3, [r0], #4
bcc La1
ldr r1,=EBI_RCB
ldr r0,=1
str r0,[r1] ;remap,do not worry about pipe line
?DATA_I_Init ;need copy DATA_ID to DATA_I
tst r8,#1 ;reg r8 is boot test flag
;ram boot
ldreq r0,=SFB(DATA_I)
ldreq r1,=SFE(DATA_I)
ldreq r2,=SFB(DATA_ID)
;flash boot
ldrne r0,=SFB(DATA_I)
ldrne r1,=SFE(DATA_I)
ldrne r2,=SFB(DATA_ID)
addne r2,r2,#0x1000000 ;flash addr is 0x1000000 after remap
La2 ;copy DATA_ID to DATA_I
cmp r0, r1
ldrcc r3, [r2], #4
strcc r3, [r0], #4
bcc La2
?DATA_Z_Init ;fill DATA_Z with 0
ldr r0,=SFB(DATA_Z)
ldr r1,=SFE(DATA_Z)
mov r3, #0
La3
cmp r0, r1
strcc r3, [r0], #4
bcc La3
;set stack for C
ldr r0, = TOP_STACK
; Set up the SYS stack pointer last and return to SVC mode
msr CPSR_c, #ARM_MODE_SYS|I_BIT|F_BIT
mov r13, r0
sub r0, r0, #SYS_STACK_SIZE
;Set up Fast Interrupt Mode and set FIQ Mode Stack
msr CPSR_c, #ARM_MODE_FIQ|I_BIT|F_BIT
mov r13, r0 ; Init stack FIQ
sub r0, r0, #FIQ_STACK_SIZE
;- Set up Interrupt Mode and set IRQ Mode Stack
msr CPSR_c, #ARM_MODE_IRQ|F_BIT
mov r13, r0 ; Init stack IRQ
sub r0, r0, #IRQ_STACK_SIZE
;- Set up Abort Mode and set Abort Mode Stack
msr CPSR_c, #ARM_MODE_ABORT|I_BIT|F_BIT
mov r13, r0 ; Init stack Abort
sub r0, r0, #ABT_STACK_SIZE
;- Set up Undefined Instruction Mode and set Undef Mode Stack
msr CPSR_c, #ARM_MODE_UNDEF|I_BIT|F_BIT
mov r13, r0 ; Init stack Undef
sub r0, r0, #UND_STACK_SIZE
msr CPSR_c, #ARM_MODE_SVC|F_BIT
mov r13, r0
ldr pc,=main
bl . ;if return from main,loop
;-------------------------------------------------------------------------------
;fast interrupt
ISR_MAC FIQ_Manual_SW,fiq_handler
;-------------------------------------------------------------------------------
;software interrupt
ISR_MAC INT_SWI,swi_irq_handler
;-------------------------------------------------------------------------------
;USART interrupt
ISR_MAC INT_USART0,usart0_handler
ISR_MAC INT_USART1,usart1_handler
;-------------------------------------------------------------------------------
;timer interrupt
ISR_MAC INT_TC0,tc0_handler
ISR_MAC INT_TC1,tc1_handler
ISR_MAC INT_TC2,tc2_handler
;-------------------------------------------------------------------------------
;wdt Controller interrupt
ISR_MAC INT_WDT,wdt_handler
;-------------------------------------------------------------------------------
;parallel I/O Controller interrupt
ISR_MAC INT_PIO,pio_handler
;-------------------------------------------------------------------------------
;external interrupt
ISR_MAC IRQ_EX0,ex0_handler
ISR_MAC IRQ_EX1,ex1_handler
ISR_MAC IRQ_EX2,ex2_handler
;-------------------------------------------------------------------------------
;SPU interrupt
ISR_MAC INT_SPU,spu_handler
;-------------------------------------------------------------------------------
;disable interrupt
EXPORT DISABLE_INT
DISABLE_INT
MRS R0,CPSR ; Set IRQ and FIQ bits in CPSR to disable all interrupts
ORR R1,R0,#NO_INT
MSR CPSR_c,R1
MOV PC,LR ; Disabled, return the original CPSR contents in R0
;-------------------------------------------------------------------------------
;enable interrupt
EXPORT ENABLE_INT
ENABLE_INT
MSR CPSR_c,R0
MOV PC,LR
EBI_Config
DCD EBI_DBW_16|EBI_NWS_4|EBI_WSE|EBI_PAGES_4M|EBI_TDF_0|EBI_BAT_BYTE_WRITE|EBI_CSEN|FLASH1_BASE ;NCS0: SST39VF160, 2MBits 70ns flash
; DCD EBI_DBW_16|EBI_NWS_2|EBI_WSE|EBI_PAGES_4M|EBI_TDF_0|EBI_BAT_BYTE_SELECT|EBI_CSEN|ETHERNET0_BASE ;NCS1: EtherNet0 88796B
; turbo mode EBI_NWS_6 normal 7 buwending
DCD EBI_DBW_16|EBI_NWS_8|EBI_WSE|EBI_PAGES_4M|EBI_TDF_0|EBI_BAT_BYTE_SELECT|EBI_CSEN|ETHERNET0_BASE ;NCS1: EtherNet0 KSZ8842M
DCD EBI_DBW_16|EBI_NWS_1|EBI_WSE|EBI_PAGES_4M|EBI_TDF_0|EBI_BAT_BYTE_SELECT|EBI_CSEN|ETHERNET1_BASE ;NCS2: Dpram SEML
DCD EBI_DBW_16|EBI_NWS_1|EBI_WSE|EBI_PAGES_1M|EBI_TDF_1|EBI_BAT_BYTE_SELECT|EBI_CSEN|EPADPRAM_BASE ;NCS3: Dpram DCD 0x40000000 ;rsv
DCD 0x40000000 ;rsv
DCD 0x50000000 ;rsv
DCD 0x60000000 ;rsv
DCD 0x70000000 ;rsv
DCD 0 ;remap
DCD EBI_ALE_16M|EBI_DRP_STANDARD ;valid A20,A21,A22,A23,standard read
DCD EBI_BASE
LTORG
ENDMOD
END
转载请注明原文出处，http://www.cnblogs.com/flyingcloude/p/6992339.html
标签：data ext rcc byte manual mode blank poi control
原文地址：http://www.cnblogs.com/flyingcloude/p/6992339.html
