uboot学习之uboot-spl的程序流程分析

...//前面省略
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
    .text      :
    {
    __start = .;
      arch/arm/cpu/armv7/start.o    (.text)
      *(.text*)
    } >.sram

    . = ALIGN(4);
    .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram

    . = ALIGN(4);
    .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
    . = ALIGN(4);
    __image_copy_end = .;
    _end = .;

    .bss :
    {
        . = ALIGN(4);
        __bss_start = .;
        *(.bss*)
        . = ALIGN(4);
        __bss_end__ = .;
    } >.sdram
}

.globl _start
_start: b    reset
    ldr    pc, _undefined_instruction
    ldr    pc, _software_interrupt
    ldr    pc, _prefetch_abort
    ldr    pc, _data_abort
    ldr    pc, _not_used
    ldr    pc, _irq
    ldr    pc, _fiq
#ifdef CONFIG_SPL_BUILD
_undefined_instruction: .word _undefined_instruction
_software_interrupt:    .word _software_interrupt
_prefetch_abort:    .word _prefetch_abort
_data_abort:        .word _data_abort
_not_used:        .word _not_used
_irq:            .word _irq
_fiq:            .word _fiq
_pad:            .word 0x12345678 /* now 16*4=64 */
#else
_undefined_instruction: .word undefined_instruction
_software_interrupt:    .word software_interrupt
_prefetch_abort:    .word prefetch_abort
_data_abort:        .word data_abort
_not_used:        .word not_used
_irq:            .word irq
_fiq:            .word fiq
_pad:            .word 0x12345678 /* now 16*4=64 */
#endif    /* CONFIG_SPL_BUILD */

.global _end_vect
_end_vect:

    .balignl 16,0xdeadbeef

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
    .word    0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
    .word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
    .word    0x0badc0de

/*
 * the actual reset code
 */

reset:
    bl    save_boot_params
    /*
     * set the cpu to SVC32 mode
     */
@    mov r0, #0
@    cmp r0, #0
@    beq reset
here:
    mrs    r0, cpsr
    bic    r0, r0, #0x1f
    orr    r0, r0, #0xd3   @switch to svc mode and disable irq/fiq
    msr    cpsr,r0

#if defined(CONFIG_ARM_A7)
@set SMP bit
    mrc     p15, 0, r0, c1, c0, 1
    orr        r0, r0, #(1<<6)
    mcr        p15, 0, r0, c1, c0, 1
#endif
@#if defined(CONFIG_ARCH_SUN9IW1P1)
@    ldr     r0, =0x008000e0
@    ldr     r1, =0x16aa0001
@    str     r1, [r0]
@#endif

void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)__attribute__((weak, alias("save_boot_params_default")));

#if defined(CONFIG_OMAP34XX)
    /* Copy vectors to mask ROM indirect addr */
    adr    r0, _start        @ r0 <- current position of code
    add    r0, r0, #4        @ skip reset vector
    mov    r2, #64            @ r2 <- size to copy
    add    r2, r0, r2        @ r2 <- source end address
    mov    r1, #SRAM_OFFSET0    @ build vect addr
    mov    r3, #SRAM_OFFSET1
    add    r1, r1, r3
    mov    r3, #SRAM_OFFSET2
    add    r1, r1, r3
next:
    ldmia    r0!, {r3 - r10}        @ copy from source address [r0]
    stmia    r1!, {r3 - r10}        @ copy to   target address [r1]
    cmp    r0, r2            @ until source end address [r2]
    bne    next            @ loop until equal */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
    /* No need to copy/exec the clock code - DPLL adjust already done
     * in NAND/oneNAND Boot.
     */
    bl    cpy_clk_code        @ put dpll adjust code behind vectors
#endif /* NAND Boot */
#endif /* CONFIG_OMAP34XX */
    /* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
    bl    cpu_init_crit
#endif

cpu_init_crit:
    /*
     * Invalidate L1 I/D
     */
    ...//省略详细的内容

    /*
     * disable MMU stuff and caches
     */
    ...//省略详细的内容

    /*
     * Jump to board specific initialization...
     * The Mask ROM will have already initialized
     * basic memory. Go here to bump up clock rate and handle
     * wake up conditions.
     */
    mov    ip, lr            @ persevere link reg across call
    bl    lowlevel_init        @ go setup pll,mux,memory
    mov    lr, ip            @ restore link
    mov    pc, lr            @ back to my caller
#endif

call_board_init_f:
    ldr    sp, =(CONFIG_SYS_INIT_SP_ADDR)
    bic    sp, sp, #7 /* 8-byte alignment for ABI compliance */
    ldr    r0,=0x00000000

    @bl  boot_standby_relocat

    bl    board_init_f