标签：style output out tput code sam always bsp logs
Code 1: Led be lighted by delay time.
module ledl(clk,led); input clk; output [3:0]led; reg [3:0]led; reg [25:0]counter; always@(posedge clk) begin counter<=counter+1; if(counter==25‘b0000000000000001111111111) led=~led; //Four led be lighted at same time. end endmodule
标签：style output out tput code sam always bsp logs
原文地址：http://www.cnblogs.com/assassinn/p/7464613.html
