Verilog MIPS32 CPU（二）-- Regfiles

module RegFiles(
        input clk,
        input rst,
        input we,
        input [4:0] raddr1,
        input [4:0] raddr2,
        input [4:0] waddr,
        input [31:0] wdata,
        output [31:0] rdata1,
        output [31:0] rdata2
        );
    
    reg [31:0] data [0:31];
    
    always@(posedge clk or posedge rst) begin
        if(rst)  for(i=0;i<32;i=i+1) begin
            data[i]<=32‘b0;
        end
        else begin
            if(we&&waddr!=5‘b0) data[waddr]<=wdata;
        end
    end
    
endmodule