embeded_2_separate_sync

  1 //如果是8位的话，只选择低8位传输
  2 //因为同步码也是可以自己设置，所以把同步码设置成parameter最好
  3 module embeded_2_separate_sync(
  4         input clk,
  5         input [15:0] din,
  6         output[15:0] dout,
  7         output h_sync_out,
  8         output v_sync_out,
  9         output h_no_sync_black_out,
 10         output h_sync_black_out,
 11         output h_sync_orign_out
 12         
 13     
 14     );          
 15     
 16     
 17     parameter DATA_WIDTH = 16;
 18     reg [DATA_WIDTH-1:0] v_data [6:0] ;
 19     
 20     always @( posedge clk )
 21     begin
 22         v_data[0] <= din; 
 23     end
 24     genvar  i  ;
 25     generate 
 26            
 27         for( i = 0;i <= 5;i = i+1 )
 28         begin :data_dly          
 29          always@( posedge clk )begin  
 30                     v_data[i+1] <= v_data[i];
 31             end
 32             assign dout = v_data[6];  
 33             
 34         end
 35     endgenerate
 36     wire [6:0] time_ref_code;
 37     reg    [6:0] time_ref_code_r = 0;
 38     assign time_ref_code [6] = (v_data[3][7:0] == 8‘hff   ) ? 1‘b1 : 1‘b0;
 39     assign time_ref_code [5] = (v_data[2][7:0] == 8‘h00 ) ? 1‘b1 : 1‘b0;
 40     assign time_ref_code [4] = (v_data[1][7:0] == 8‘h00 ) ? 1‘b1 : 1‘b0;
 41     assign    time_ref_code[0] =     (v_data[0][7:0] ==8‘h80) ?1‘b1 : 1‘b0;
 42     assign    time_ref_code[1] =     (v_data[0][7:0] ==8‘h9d) ?1‘b1 : 1‘b0;
 43     assign    time_ref_code[2] =     (v_data[0][7:0] ==8‘hab) ?1‘b1 : 1‘b0;
 44     assign    time_ref_code[3] =     (v_data[0][7:0] ==8‘hb6) ?1‘b1 : 1‘b0;
 45 
 46     
 47     always @( posedge clk )
 48     begin
 49             time_ref_code_r <= time_ref_code;
 50     end
 51     
 52 //    reg h_sync;
 53 //    reg v_sync;
 54     reg    h_sync_r = 0;
 55     reg    v_sync_r = 0;
 56     always @( posedge clk  )
 57     begin
 58             case(time_ref_code_r )
 59                 7‘h71 :begin  h_sync_r = 1‘b0; v_sync_r = 1‘b0; end
 60                 7‘h72 :begin  h_sync_r = 1‘b1; v_sync_r = 1‘b0; end
 61                 7‘h74 :begin  h_sync_r = 1‘b0; v_sync_r = 1‘b1; end
 62                 7‘h78 :begin  h_sync_r = 1‘b1; v_sync_r = 1‘b1; end
 63                 default : begin h_sync_r = h_sync_r; v_sync_r = v_sync_r; end
 64             endcase
 65     end
 66     
 67     reg [3:0] h_sync_dly = 0;
 68     reg [3:0] v_sync_dly = 0;
 69     always @( posedge clk )
 70     begin
 71             h_sync_dly[3:0] <= {h_sync_dly[2:0],h_sync_r};
 72             v_sync_dly[3:0] <= {v_sync_dly[2:0],v_sync_r};
 73     end
 74     
 75     wire h_black ;
 76     wire h_no_sync_black;
 77     wire h_sync_black;
 78     reg h_black_r = 0;
 79     reg v_black_r = 0;
 80     reg h_no_sync_black_r = 0;
 81     reg h_sync_black_r = 0;
 82     reg h_sync_orign_r = 0;
 83     assign h_black = h_sync_r | h_sync_dly[3] ;
 84     assign h_no_sync_black =  h_sync_r & h_sync_dly[3] ;
 85     assign h_sync_black = h_black^h_no_sync_black ;
 86     always @( posedge clk )
 87     begin
 88             h_black_r <= h_black;
 89             v_black_r <= v_sync_r;
 90             h_no_sync_black_r <= h_no_sync_black;
 91             h_sync_black_r <= h_sync_black;
 92             h_sync_orign_r <= h_sync_r;
 93     end
 94     
 95     
 96     
 97     
 98     assign h_sync_out = h_black_r;
 99     assign v_sync_out = v_black_r;
100     assign h_no_sync_black_out = h_no_sync_black_r;
101     assign h_sync_black_out = h_sync_black_r;
102     assign h_sync_orign_out = h_sync_orign_r;
103     endmodule