实现1sym转换成2个sym送给CVI（VGA数据）

CVI的时序如下 ：de指示数据有效。

  1     module vga_1sym_2_2sym(
  2     input clk_i,
  3     input rst_p,
  4     input [15:0] data_i,
  5     input h_sync_i,  
  6     input v_sync_i,    
  7     input de_i ,
  8     
  9     output [31:0] data_o,
 10     output [1:0] h_sync_o,
 11     output [1:0] v_sync_o,
 12     output [1:0] de_o,
 13     output vga_clk_o
 14     
 15     );
 16     
 17     
 18     
 19  
 20  wire ctrl_clk;    
 21   wire vga_clk;
 22   wire vga_clk_dvi2;
 23   clkctrl u0_clkctrl (
 24         .inclk  (clk_i),  //  altclkctrl_input.inclk
 25         .outclk (ctrl_clk)  // altclkctrl_output.outclk
 26     );
 27     iopll u0 (
 28         .rst      (rst_p),      //   reset.reset
 29         .refclk   (ctrl_clk),   //  refclk.clk
 30         .locked   (),   //  locked.export
 31         .outclk_0 (vga_clk),  // outclk0.clk
 32         .outclk_1 (vga_clk_dvi2)  // outclk0.clk
 33     );     
 34     
 35     
 36     reg [15:0] data_r;
 37     reg [15:0] vga_data_dly2;
 38     reg [15:0] vga_data_dly3;
 39     reg h_sync_r = 0;
 40     reg v_sync_r = 0;
 41     reg de_r  = 0;
 42     always @( posedge vga_clk )
 43     begin
 44             data_r <= data_i;
 45             h_sync_r <= h_sync_i;
 46             v_sync_r <= v_sync_i;
 47             de_r <= de_i;
 48     end
 49 //    reg [1:0] de_dly = 2‘b00;
 50 //    always @( posedge vga_clk )
 51 //    begin
 52 //                    de_dly[1:0] <= {de_dly[0],de_i};
 53 //    end
 54 //    wire pos_de = (de_dly[1:0] == 2‘b01 );
 55     reg h_l_cnt = 1‘b0;
 56     always @( posedge vga_clk )
 57     begin
 58 //            if( pos_de )
 59 //                    h_l_cnt <= 1‘b1;
 60 //            else
 61                     h_l_cnt <= ~h_l_cnt;
 62     end
 63     reg [31:0]data_r2 = 0;
 64     reg [1:0] h_sync_r2 = 2‘b00;
 65     reg [1:0] v_sync_r2 = 2‘b00;
 66     reg [1:0] de_r2 = 2‘b00;
 67     always @( posedge vga_clk )
 68     begin
 69             if( h_l_cnt ) begin
 70                     data_r2[15:0] <= data_r;
 71                     h_sync_r2[0] <= h_sync_r;
 72                     v_sync_r2[0] <= v_sync_r;
 73                     de_r2[0] <= de_r;
 74                     
 75                     
 76             end else begin
 77                     
 78                     data_r2[31:16] <= data_r;
 79                     h_sync_r2[1] <= h_sync_r;
 80                     v_sync_r2[1] <= v_sync_r;
 81                     de_r2[1] <= de_r;
 82             end
 83     end
 84     reg vga_cvi_valid = 0;
 85     always @( posedge vga_clk )
 86     begin
 87             if( ~h_l_cnt )
 88                     vga_cvi_valid <= 1‘b1;
 89             else
 90                     vga_cvi_valid <= 1‘b0;        
 91             
 92     end
 93     
 94 //    assign data_o = data_r2;
 95 //    assign h_sync_o = h_sync_r2;
 96 //    assign v_sync_o = v_sync_r2;
 97 //    assign de_o = de_r2;
 98     
 99    wire rd_empty;  
100    wire [37:0] fifo_dout; 
101    reg [1:0] rd_empty_r = 2‘b00;  
102    wire rd_en ;
103     fifo_w22 u0_fifo_w22 (
104         .data    ({data_r2,h_sync_r2,v_sync_r2,de_r2}),    //  fifo_input.datain
105         .wrreq   (vga_cvi_valid),   //            .wrreq
106         .rdreq   (rd_en),   //            .rdreq
107         .wrclk   (vga_clk),   //            .wrclk
108         .rdclk   (vga_clk_dvi2),   //            .rdclk
109         .q       (fifo_dout),       // fifo_output.dataout
110         .rdempty (rd_empty), //            .rdempty
111         .wrfull  ()   //            .wrfull
112     );
113     always @( posedge vga_clk_dvi2 )
114     begin
115             rd_empty_r <= {rd_empty_r[0],rd_empty};
116     end
117     assign rd_en =  ~rd_empty_r[1];
118     assign {data_o,h_sync_o,v_sync_o,de_o} = fifo_dout;
119     assign vga_clk_o = vga_clk_dvi2;
120     endmodule
121