Verilog/VHDL Synthesis (even just for FPGA) Static Timing (setup time/hold time) Back-annotated gate level simulation Basic digital design concepts (FSM, data pipelines, etc.) Basic UNIX skills, emacs/vim, grep, find, man Basic programming (C, C++, perl, shell scripting) BS degree I expect more from an MS (at least some of the following): Verification methodology Vera/SystemVerilog/SystemC Assertions Functional Coverage Fault Coverage (scan, custom patterns) Power considerations Clock domain crossings Deep sub-micron Static timing considerations (OCV) Understanding of basic common architectures (SPI, UART, I2C, microprocessors (x86/arm/arc/powerpc) Standard cell library construction Clock tree design Reset synchronization Clock gating Basic resources (DDR DRAM, SRAM, PLL, DLL, etc.) Fifo design Clock divider design
