实现两个sym转一个sym

    module sym2_2_sym1(
    input clk_i,
    input [1:0] h_sync_i,
    input [1:0] v_sync_i,
    input [1:0] de_i,
    input [31:0] vin,  
    
    input clk_o,
    output h_sync_o,
    output v_sync_o,
    output [15:0] vout
    );
    reg de_i_r = 1‘b0;
    reg cnt = 1‘b0;
  reg [31:0] din_r = 32‘d0;
  reg [1:0] h_sync_i_r = 2‘b00;
  reg [1:0] v_sync_i_r = 2‘b00; 
  reg h_sync_r =0;
  reg v_sync_r = 0;
  reg [15:0] vout_r =0;
/*********************************************************
检测de信号上升沿，用于指示每行第一个有效数据
**********************************************************/
    always @( posedge clk_o )
    begin
        de_i_r <= de_i[0];
    
    end
    wire pos_de = ({de_i_r,de_i[0] } == 2‘b01 );
    always @( posedge clk_o )
    begin
            cnt <= pos_de ? 0 : ~cnt;
            
    end
/********************************************************* 
由于de上升沿延时一个时钟周期，所以对数据也延时一个时钟周期               
**********************************************************/
    always @( posedge clk_o )
    begin
        din_r <= vin;  
        h_sync_i_r <= h_sync_i;
        v_sync_i_r <= v_sync_i;
    end
/********************************************************* 
2转1             
**********************************************************/


    always @( posedge clk_o )
    begin
            vout_r <= cnt ? din_r[31:16] : din_r[15:0];
            h_sync_r <= cnt ? h_sync_i_r[1]: h_sync_i_r[0];
            v_sync_r <= cnt ? v_sync_i_r[1] : v_sync_i_r[0];
    end
    
    assign h_sync_o = h_sync_r;
    assign v_sync_o = v_sync_r;
    assign vout = vout_r;
    
    

    
    endmodule

module seperate_2_embeded(
    input clk,
    input h_sync,//低电平有效
    input v_sync,//低电平为有效区间
    input f_sync,
    input [9:0] h_black_len,
    input [15:0] vin,
    output [15:0] vout

);
    
    reg [5:0] h_r = 0;
    reg [5:0] v_r = 0;
    reg [15:0] vin_r1 = 0;
    reg [15:0] vin_r2 = 0;
    reg [15:0] vout_r = 0; 
    (*keep*)reg [3:0] cnt = 0;  
    wire [9:0] xyz ;
    wire black_len_m4;  
    reg black_len_m4_dly = 1‘b0;
/************************************************************************
把行消隐区间的长度去掉4个
************************************************************************/
    always @( posedge clk )
    begin
        h_r <= {h_r[4:0],h_sync};
        v_r <= {v_r[4:0],v_sync};
    end
    assign black_len_m4 = h_r[3] & h_sync;
/************************************************************************
找到上升沿与下降沿，即SAV与EAV的位置
************************************************************************/    
    always @( posedge clk )
    begin
            black_len_m4_dly <= black_len_m4;
    end
    
    assign pos_black_len_m4 = {black_len_m4_dly,black_len_m4} == 2‘b01;
    assign neg_black_len_m4 = {black_len_m4_dly,black_len_m4} == 2‘b10;
/************************************************************************
在SAV 和EAV位置计数
************************************************************************/        
    always @( posedge clk )
    begin
            if( pos_black_len_m4 | neg_black_len_m4 )
                    cnt <= 0;
            else if( cnt == 5 )
                    cnt <= cnt;
            else
                    cnt <= cnt + 1‘b1;
    end   
    

    always @( posedge clk )
    begin
            case( cnt )
            4‘h0 :
                    vout_r <= 16‘hffff;
            4‘h1 : 
                    vout_r <= 16‘h0000;
            4‘h2 :
                    vout_r <= 16‘h0000;
            4‘h3 :
                    vout_r <= {2{xyz[9:2]}};
            default:vout_r <= data[4];
            endcase
            
    end
    
    
     reg[15:0] data[4:0];
     reg [2:0] i;
    generate
      //   genvar i;
         always @( posedge clk )
         begin
                 for(i = 0;i <= 3;i= i + 1)
                         data[i+1] <= data[i];
         end
         
   endgenerate
   
        always @( posedge clk )
    begin
            data[0] <= vin;
    end
    
    
assign xyz = calc_xyz({1‘b0,v_r[0],h_r[0]});
assign vout = vout_r;
function [9:0] calc_xyz;
  input [2:0] FVH;
  case (FVH)
    3‘b000 : calc_xyz = 10‘h200;
    3‘b001 : calc_xyz = 10‘h274;
    3‘b010 : calc_xyz = 10‘h2ac;
    3‘b011 : calc_xyz = 10‘h2d8;
    3‘b100 : calc_xyz = 10‘h31c;
    3‘b101 : calc_xyz = 10‘h368;
    3‘b110 : calc_xyz = 10‘h3b0;
    3‘b111 : calc_xyz = 10‘h3c4;
  endcase
endfunction






endmodule