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23.5.1 Common registers

USB control register (USB_CNTR)

技术分享图片

Bit 15 CTRM: Correct transfer interrupt mask
  0: Correct Transfer (CTR) Interrupt disabled.
  1: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set.

Bit 14 PMAOVRM: Packet memory area over / underrun interrupt mask

Bit 13 ERRM: Error interrupt mask

Bit 12 WKUPM: Wakeup interrupt mask

Bit 11 SUSPM: Suspend mode interrupt mask

Bit 10 RESETM: USB reset interrupt mask

Bit 9 SOFM: Start of frame interrupt mask

Bit 8 ESOFM: Expected start of frame interrupt mask

Bits 7:5 Reserved.

Bit 4 RESUME: Resume request 
The microcontroller can set this bit to send a Resume signal to the host. It must be activated, according to USB specifications, for no less than 1 mS and no more than 15 mS after which the Host PC is ready to drive the resume sequence up to its end. 

Bit 3 FSUSP: Force suspend
Software must set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3 mS.
  0: No effect.
  1: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected. If suspend power consumption is a requirement (bus-powered device), the application software should set the LP_MODE bit after FSUSP as explained below.

Bit 2 LP_MODE: Low-power mode
This mode is used when the suspend-mode power constraints require that all static power dissipation is avoided, except the one required to supply the external pull-up resistor. This condition should be entered when the application is ready to stop all system clocks, or reduce their frequency in order to meet the power consumption requirements of the USB suspend condition. The USB activity during the suspend mode (WKUP event) asynchronously resets this bit (it can also be reset by software).
  0: No Low-power mode.
  1: Enter Low-power mode

Bit 1 PDWN: Power down
This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used.
  0: Exit Power Down.
  1: Enter Power down mode.

Bit 0 FRES: Force USB Reset
  0: Clear USB reset.
  1: Force a reset of the USB peripheral, exactly like a RESET signalling on the USB. The USB peripheral is held in RESET state until software clears this bit. A “USB-RESET” interrupt is generated, if enabled.

 

 

 

 

 

 

USB

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原文地址:https://www.cnblogs.com/qiyuexin/p/9038289.html

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