重学Verilog(1)

1 module  WO(A, B, C, D, WireOR)
2 input A,B,C,D;
3 output WireOr;
4 wor WireOr;
5 assign WireOr = A^B;
6 assign WireOr = C&D;
7 endmodule

assign WireTri = (En) ? 1‘bZ : (A^V)

module DEF(D, Clr, Clk, Q)
input D, Clr, Clk;
output Q;
reg Q;

always @ (Clr) begin
    if (!Clr)
        assign Q = 0;
    else
        deassign Q;
end

always @ (negedge Clk)
    Q <= D;
endmodule

initial
fork
DataBin = 0;
# 6 DataBin = 0;
# 4 DataBin = 1;
# 2 DataBin = 0;
join