基于PWM的呼吸灯设计(Verilog版)

module Breath_Led(clk,rst,led);
input clk,rst;
output reg led;
reg[19:0] count;
reg[19:0] duty_cycle;
always @(posedge clk)
begin
    if(!rst)
    begin
        led<=1‘b0;
        count<=1‘b0;
    end
    else
    begin
        if(count<20‘d999_999)
        begin
            count<=count+1‘b1;
            if(count<duty_cycle)
                led<=1‘b1;
            else
                led<=1‘b0;
        end
        else
            count<=1‘b0;
    end
end
reg flag;
always @(posedge led)
begin
    if(!rst)
    begin
        duty_cycle<=1‘b1;
        flag<=1‘b0;
    end
    else
    begin
        if(flag==1‘b0)
        begin
            if(duty_cycle<20‘d979_511)
            begin
                duty_cycle<=duty_cycle+15‘d9990;
                flag<=1‘b0;
            end
            else
            begin
                duty_cycle<=duty_cycle-15‘d9990;
                flag<=1‘b1;
            end
        end
        else
        begin
            if(duty_cycle>1‘b1)
            begin
                duty_cycle<=duty_cycle-15‘d9990;
                flag<=1‘b1;
            end
            else
            begin
                duty_cycle<=duty_cycle+15‘d9990;
                flag<=1‘b0;
            end
        end
    end
end
endmodule