[原创]Modelsim后仿真

时间：2018-12-19 13:20:54 阅读：177 评论：0 收藏：0 [点我收藏+]

标签：out cal parameter pack abs design 分享 ack iter

因调试需要，进行后仿真，ISE生成的sim文件和sdf文件

 
`timescale 1 ns/1 ps

module lut_dly (
  clkout, fpga_clk, config_in
);
  output clkout;
  input fpga_clk;
  input [5 : 0] config_in;
  wire clk_in;
  wire dly1;
  wire config_in_4_IBUF_49;
  wire config_in_5_IBUF_50;
  wire dly2_0;
  wire dly3;
  wire config_in_2_IBUF_53;
  wire config_in_3_IBUF_54;
  wire dly4_0;
  wire dly5;
  wire config_in_0_IBUF_57;
  wire config_in_1_IBUF_58;
  wire dly2;
  wire dly1_pack_1;
  wire dly4;
  wire dly3_pack_1;
  wire clkout_OBUF_129;
  wire dly5_pack_1;
  wire \config_in<0>/INBUF ;
  wire \config_in<1>/INBUF ;
  wire \config_in<2>/INBUF ;
  wire \config_in<3>/INBUF ;
  wire \config_in<4>/INBUF ;
  wire \config_in<5>/INBUF ;
  wire \clkout/O ;
  wire \fpga_clk/INBUF ;
  wire VCC;
  initial $sdf_annotate("lut_dly_timesim.sdf");
  X_BUF #(
    .LOC ( "SLICE_X88Y0" ))
  \dly2/XUSED  (
    .I(dly2),
    .O(dly2_0)
  );
  X_BUF #(
    .LOC ( "SLICE_X88Y0" ))
  \dly2/YUSED  (
    .I(dly1_pack_1),
    .O(dly1)
  );
  X_LUT4 #(
    .INIT ( 16‘h8888 ),
    .LOC ( "SLICE_X88Y0" ))
  u_lut6 (
    .ADR0(clk_in),
    .ADR1(config_in_5_IBUF_50),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(dly1_pack_1)
  );
  X_BUF #(
    .LOC ( "SLICE_X88Y1" ))
  \dly4/XUSED  (
    .I(dly4),
    .O(dly4_0)
  );
  X_BUF #(
    .LOC ( "SLICE_X88Y1" ))
  \dly4/YUSED  (
    .I(dly3_pack_1),
    .O(dly3)
  );
  X_LUT4 #(
    .INIT ( 16‘h3C0C ),
    .LOC ( "SLICE_X88Y1" ))
  u_lut4 (
    .ADR0(VCC),
    .ADR1(dly2_0),
    .ADR2(config_in_3_IBUF_54),
    .ADR3(clk_in),
    .O(dly3_pack_1)
  );
  X_BUF #(
    .LOC ( "SLICE_X89Y0" ))
  \clkout_OBUF/YUSED  (
    .I(dly5_pack_1),
    .O(dly5)
  );
  X_LUT4 #(
    .INIT ( 16‘h3838 ),
    .LOC ( "SLICE_X89Y0" ))
  u_lut2 (
    .ADR0(clk_in),
    .ADR1(config_in_1_IBUF_58),
    .ADR2(dly4_0),
    .ADR3(VCC),
    .O(dly5_pack_1)
  );
  X_IPAD #(
    .LOC ( "PAD685" ))
  \config_in<0>/PAD  (
    .PAD(config_in[0])
  );
  X_BUF #(
    .LOC ( "PAD685" ))
  config_in_0_IBUF (
    .I(config_in[0]),
    .O(\config_in<0>/INBUF )
  );
  X_BUF #(
    .LOC ( "PAD685" ))
  \config_in<0>/IFF/IMUX  (
    .I(\config_in<0>/INBUF ),
    .O(config_in_0_IBUF_57)
  );
  X_IPAD #(
    .LOC ( "PAD686" ))
  \config_in<1>/PAD  (
    .PAD(config_in[1])
  );
  X_BUF #(
    .LOC ( "PAD686" ))
  config_in_1_IBUF (
    .I(config_in[1]),
    .O(\config_in<1>/INBUF )
  );
  X_BUF #(
    .LOC ( "PAD686" ))
  \config_in<1>/IFF/IMUX  (
    .I(\config_in<1>/INBUF ),
    .O(config_in_1_IBUF_58)
  );
  X_IPAD #(
    .LOC ( "PAD683" ))
  \config_in<2>/PAD  (
    .PAD(config_in[2])
  );
  X_BUF #(
    .LOC ( "PAD683" ))
  config_in_2_IBUF (
    .I(config_in[2]),
    .O(\config_in<2>/INBUF )
  );
  X_BUF #(
    .LOC ( "PAD683" ))
  \config_in<2>/IFF/IMUX  (
    .I(\config_in<2>/INBUF ),
    .O(config_in_2_IBUF_53)
  );
  X_IPAD #(
    .LOC ( "PAD681" ))
  \config_in<3>/PAD  (
    .PAD(config_in[3])
  );
  X_BUF #(
    .LOC ( "PAD681" ))
  config_in_3_IBUF (
    .I(config_in[3]),
    .O(\config_in<3>/INBUF )
  );
  X_BUF #(
    .LOC ( "PAD681" ))
  \config_in<3>/IFF/IMUX  (
    .I(\config_in<3>/INBUF ),
    .O(config_in_3_IBUF_54)
  );
  X_IPAD #(
    .LOC ( "PAD688" ))
  \config_in<4>/PAD  (
    .PAD(config_in[4])
  );
  X_BUF #(
    .LOC ( "PAD688" ))
  config_in_4_IBUF (
    .I(config_in[4]),
    .O(\config_in<4>/INBUF )
  );
  X_BUF #(
    .LOC ( "PAD688" ))
  \config_in<4>/IFF/IMUX  (
    .I(\config_in<4>/INBUF ),
    .O(config_in_4_IBUF_49)
  );
  X_IPAD #(
    .LOC ( "PAD682" ))
  \config_in<5>/PAD  (
    .PAD(config_in[5])
  );
  X_BUF #(
    .LOC ( "PAD682" ))
  config_in_5_IBUF (
    .I(config_in[5]),
    .O(\config_in<5>/INBUF )
  );
  X_BUF #(
    .LOC ( "PAD682" ))
  \config_in<5>/IFF/IMUX  (
    .I(\config_in<5>/INBUF ),
    .O(config_in_5_IBUF_50)
  );
  X_OPAD #(
    .LOC ( "PAD680" ))
  \clkout/PAD  (
    .PAD(clkout)
  );
  X_OBUF #(
    .LOC ( "PAD680" ))
  clkout_OBUF (
    .I(\clkout/O ),
    .O(clkout)
  );
  X_IPAD #(
    .LOC ( "PAD684" ))
  \fpga_clk/PAD  (
    .PAD(fpga_clk)
  );
  X_BUF #(
    .LOC ( "PAD684" ))
  u_ibufg (
    .I(fpga_clk),
    .O(\fpga_clk/INBUF )
  );
  X_BUF #(
    .LOC ( "PAD684" ))
  \fpga_clk/IFF/IMUX  (
    .I(\fpga_clk/INBUF ),
    .O(clk_in)
  );
  X_LUT4 #(
    .INIT ( 16‘h0FA0 ),
    .LOC ( "SLICE_X88Y0" ))
  u_lut5 (
    .ADR0(clk_in),
    .ADR1(VCC),
    .ADR2(config_in_4_IBUF_49),
    .ADR3(dly1),
    .O(dly2)
  );
  X_LUT4 #(
    .INIT ( 16‘h3C30 ),
    .LOC ( "SLICE_X88Y1" ))
  u_lut3 (
    .ADR0(VCC),
    .ADR1(config_in_2_IBUF_53),
    .ADR2(dly3),
    .ADR3(clk_in),
    .O(dly4)
  );
  X_LUT4 #(
    .INIT ( 16‘h0AF0 ),
    .LOC ( "SLICE_X89Y0" ))
  u_lut1 (
    .ADR0(clk_in),
    .ADR1(VCC),
    .ADR2(dly5),
    .ADR3(config_in_0_IBUF_57),
    .O(clkout_OBUF_129)
  );
  X_BUF #(
    .LOC ( "PAD680" ))
  \clkout/OUTPUT/OFF/OMUX  (
    .I(clkout_OBUF_129),
    .O(\clkout/O )
  );
  X_ONE   NlwBlock_lut_dly_VCC (
    .O(VCC)
  );
endmodule


`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1‘bz;
    reg JTAG_USER_TDO2_GLBL = 1‘bz;
    reg JTAG_USER_TDO3_GLBL = 1‘bz;
    reg JTAG_USER_TDO4_GLBL = 1‘bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
    GSR_int = 1‘b1;
    PRLD_int = 1‘b1;
    #(ROC_WIDTH)
    GSR_int = 1‘b0;
    PRLD_int = 1‘b0;
    end

    initial begin
    GTS_int = 1‘b1;
    #(TOC_WIDTH)
    GTS_int = 1‘b0;
    end

endmodule

SDF文件

(DELAYFILE
  (SDFVERSION "3.0")
  (DESIGN "lut_dly")
  (DATE "Sun Mar 22 15:04:04 2015")
  (VENDOR "Xilinx")
  (PROGRAM "Xilinx SDF Writer")
  (VERSION "K.31")
  (DIVIDER /)
  (VOLTAGE 1.425)
  (TEMPERATURE 85)
  (TIMESCALE 1 ps)
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE dly2\/XUSED)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 111 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE dly2\/YUSED)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 111 ))
        )
      )
  )
  (CELL (CELLTYPE "X_LUT4")
    (INSTANCE u_lut6)
      (DELAY
        (ABSOLUTE
          (PORT ADR0 ( 676 ))
          (PORT ADR1 ( 593 ))
          (IOPATH ADR0 O ( 236 ))
          (IOPATH ADR1 O ( 236 ))
          (IOPATH ADR2 O ( 236 ))
          (IOPATH ADR3 O ( 236 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE dly4\/XUSED)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 111 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE dly4\/YUSED)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 111 ))
        )
      )
  )
  (CELL (CELLTYPE "X_LUT4")
    (INSTANCE u_lut4)
      (DELAY
        (ABSOLUTE
          (PORT ADR1 ( 367 ))
          (PORT ADR2 ( 454 ))
          (PORT ADR3 ( 483 ))
          (IOPATH ADR0 O ( 236 ))
          (IOPATH ADR1 O ( 236 ))
          (IOPATH ADR2 O ( 236 ))
          (IOPATH ADR3 O ( 236 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE clkout_OBUF\/YUSED)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 111 ))
        )
      )
  )
  (CELL (CELLTYPE "X_LUT4")
    (INSTANCE u_lut2)
      (DELAY
        (ABSOLUTE
          (PORT ADR0 ( 676 ))
          (PORT ADR1 ( 409 ))
          (PORT ADR2 ( 4 ))
          (IOPATH ADR0 O ( 236 ))
          (IOPATH ADR1 O ( 236 ))
          (IOPATH ADR2 O ( 236 ))
          (IOPATH ADR3 O ( 236 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in_0_IBUF)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 71 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in\<0\>\/IFF\/IMUX)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 501 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in_1_IBUF)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 73 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in\<1\>\/IFF\/IMUX)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 501 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in_2_IBUF)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 75 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in\<2\>\/IFF\/IMUX)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 501 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in_3_IBUF)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 52 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in\<3\>\/IFF\/IMUX)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 501 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in_4_IBUF)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 54 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in\<4\>\/IFF\/IMUX)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 501 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in_5_IBUF)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 51 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE config_in\<5\>\/IFF\/IMUX)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 501 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OBUF")
    (INSTANCE clkout_OBUF)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 3308 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE u_ibufg)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 71 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE fpga_clk\/IFF\/IMUX)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 501 ))
        )
      )
  )
  (CELL (CELLTYPE "X_LUT4")
    (INSTANCE u_lut5)
      (DELAY
        (ABSOLUTE
          (PORT ADR0 ( 647 ))
          (PORT ADR2 ( 540 ))
          (PORT ADR3 ( 2 ))
          (IOPATH ADR0 O ( 236 ))
          (IOPATH ADR1 O ( 236 ))
          (IOPATH ADR2 O ( 236 ))
          (IOPATH ADR3 O ( 236 ))
        )
      )
  )
  (CELL (CELLTYPE "X_LUT4")
    (INSTANCE u_lut3)
      (DELAY
        (ABSOLUTE
          (PORT ADR1 ( 616 ))
          (PORT ADR2 ( 28 ))
          (PORT ADR3 ( 452 ))
          (IOPATH ADR0 O ( 236 ))
          (IOPATH ADR1 O ( 236 ))
          (IOPATH ADR2 O ( 236 ))
          (IOPATH ADR3 O ( 236 ))
        )
      )
  )
  (CELL (CELLTYPE "X_LUT4")
    (INSTANCE u_lut1)
      (DELAY
        (ABSOLUTE
          (PORT ADR0 ( 647 ))
          (PORT ADR2 ( 28 ))
          (PORT ADR3 ( 511 ))
          (IOPATH ADR0 O ( 236 ))
          (IOPATH ADR1 O ( 236 ))
          (IOPATH ADR2 O ( 236 ))
          (IOPATH ADR3 O ( 236 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE clkout\/OUTPUT\/OFF\/OMUX)
      (DELAY
        (PATHPULSE (605))
        (ABSOLUTE
          (IOPATH I O ( 853 ))
        )
      )
  )
)

顶层仿真文件

`timescale 1ns / 1ps
module tb_dly;
reg clk_in;
reg [5:0] sel_in;
wire clk_out;
lut_dly uut(
               .fpga_clk (clk_in ),
               .config_in (sel_in ),
               .clkout(clk_out)
                  );
                  
initial 
begin
    clk_in =0;

    #1000        
    sel_in = 6‘d32;     
    #1000 
    sel_in = 6‘d16; 
    #1000 
    sel_in = 6‘d8;      
    #1000 
    sel_in = 6‘d4; 
    #1000       
    sel_in = 6‘d2;    
    #1000     
    sel_in = 6‘d1;         
  
end

always #(5/2)  clk_in <= ~clk_in;
endmodule

do文件

vlib work 
vlog +acc tb_dly.v
 
vlog +acc lut_dly_timesim.v
vlog +acc C:/Xilinx/ISE/verilog/src/glbl.v
vsim -novopt -t 1ps -L UNISIMS_VER -L UNIMACRO_VER -L UNI9000_VER -L SIMPRIMS_VER -L XILINXCORELIB_VER -L SECUREIP -L AIM_VER -L CPLD_VER -L UNISIM -L UNIMACRO -L SIMPRIM -L XILINXCORELIB -L AIM -L PLS -L CPLD -lib work tb_dly glbl
log -r /*

Modelsim仿真波形如下

技术分享图片