Verilog实现同步FIFO

//this program segment realize the function of fifo IPcore
//synchronous fifo
module fifo_ip 
#( parameter Addr_Width=8,Bit_Width=8
)
(clk,rst,wren,rden,full,empty,din,dout,counter);
input clk,rst,wren,rden;
input[Bit_Width-1:0] din;
output full,empty;
output reg[Bit_Width-1:0] dout;
output reg[2:0] counter;
reg[3:0] addr_wr,addr_rd;
reg[Bit_Width-1:0] buf_mem[0:Addr_Width-1];
parameter s0=2‘b00,s1=2‘b01,s2=2‘b10,s3=2‘b11;
always @(posedge clk or negedge rst)
begin
if(!rst)
    begin
        dout<=0;
        counter<=0;
        addr_wr<=0;
        addr_rd<=0;
    end
else
    begin
        case({rden,wren})
        s1:begin
                if(!full)
                    begin
                        buf_mem[addr_wr]<=din;
                        addr_wr<=addr_wr+1;
                        counter<=counter+1;
                    end
            end
        s2:begin
                if(!empty)
                    begin
                        dout<=buf_mem[addr_rd];
                        addr_rd<=addr_rd+1;
                        counter<=counter-1;
                    end
            end
        s3:begin
                if(!empty)
                    begin
                        dout<=buf_mem[addr_rd];
                        addr_rd<=addr_rd+1;
                        if(full) counter<=counter-1;
                    end
                if(!full)
                    begin
                        buf_mem[addr_wr]<=din;
                        addr_wr<=addr_wr+1;
                        if(empty) counter<=counter+1;
                    end
            end
        endcase
    end
end
assign full=({~addr_wr[3],addr_wr[2:0]}==addr_rd[3:0])?1:0;
assign empty=(addr_rd[3:0]==addr_wr[3:0])?1:0;
endmodule