三段式有限状态机Verilog代码

module FSM(
    input clk,
    input clr,
    input x,
    output reg z,
    output reg [1:0] current_state,next_state
    );//101序列检测器；
//FSM中主要包含现态CS、次态NS、输出逻辑OL；
    parameter S0=2‘b00,S1=2‘b01,S2=2‘b11,S3=2‘b10;//状态编码，采用格雷编码方式，S0为IDLE；

/*------------------次态和现态的转换---------------*/    
always @(posedge clk or negedge clr) begin
        if(clr)
            current_state<=S0;
        else
            current_state<=next_state

end
 
/*------------------现态在输入情况下转换为次态的组合逻辑---------------*/    
    always @(current_state or x) begin
        case(current_state)
            S0:begin 
                if(x)
                    next_state<=S1;
                else 
                    next_state<=S0;
            end
            S1:begin
                if(x)
                    next_state<=S1;
                else 
                    next_state<=S2;            
            end
            S2:begin
                if(x)
                    next_state<=S3;
                else 
                    next_state<=S0;            
            end
            S3:begin
                if(x)
                    next_state<=S1;
                else 
                    next_state<=S2;            
            end
            default:next_state<=S0; 
        endcase
    end
/*------------------现态到输出的组合逻辑---------------*/         
        always @(current_state) begin
            case(current_state)//从S3要变化到S2这一刻；
                S3:z=1‘b1;
                default:z=1‘b0;
            endcase  
        end            
endmodule