标签：always 一个 output com ase http div 完成 code
此次任务的主要目标是完成之前三次的仿真任务以及uart协议串口接收的代码编写，仿真还是花了不少时间的，因为仿真用的板子是ego1，利用vivado来下板子，之前一直是通过ise在basys3上完成板级实验，要说的是，ego1提供的是100mhz的频率时钟，所以需要一个时钟分频来校对
100hz转25hz：
module c100_25(
input clk_100mhz,
input rst_n,
output reg clk_25m
);
reg cnt;
always@(posedge clk_100mhz or negedge rst_n)
begin
if(!rst_n)
clk_25m <= 1‘b0;
else if(cnt == 1‘b1)
clk_25m <= ~clk_25m;
else
clk_25m <= clk_25m;
end
always@(posedge clk_100mhz or negedge rst_n)
begin
if(!rst_n)
cnt <= 1‘b0;
else
cnt <= cnt + 1‘b1;
end
endmodule
100hz转50hz：
module c100_50(
input clk_100mhz,
input rst_n,
output reg clk
);
always@(posedge clk_100mhz or negedge rst_n)
begin
if(!rst_n)
clk <= 1‘b0;
else
clk <= ~clk;
end
endmodule
uart协议串口接收：
module js(
input clk_100mhz,
input rst_n,
input [2:0]baud_set,
input rx,
output reg [7:0]data_byte,
output reg rx_done
);
wire clk;
c100_50 a(
.clk_100mhz(clk_100mhz),
.rst_n(rst_n),
.clk(clk)
);
reg s0_rx,s1_rx;// 同步寄存器
reg tmp0_rx,tmp1_rx; // 数据寄存器
reg [2:0] r_data_byte [7:0];
reg [15:0]bps_dr;
reg [15:0]div_cnt;
reg state;
reg bps_clk;
reg [7:0]bps_cnt;
wire nedege;
reg [2:0] stop_bit,start_bit;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
s0_rx <= 1‘b0;
s1_rx <= 1‘b0;
end
else
begin
s0_rx <= rx;
s1_rx <= s0_rx;
end
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
tmp0_rx <= 1‘b0;
tmp1_rx <= 1‘b0;
end
else
begin
tmp0_rx <= s1_rx;
tmp1_rx <= tmp0_rx;
end
end
assign nedege = tmp0_rx & tmp1_rx;
//波特率选择
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
bps_dr <= 16‘d324;
else
case(baud_set)
0: bps_dr <= 16‘d324;
1: bps_dr <= 16‘d162;
2: bps_dr <= 16‘d80;
3: bps_dr <= 16‘d53;
4: bps_dr <= 16‘d26;
default: bps_dr <= 16‘d324;
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
div_cnt <= 16‘d0;
else if(state) begin
if (div_cnt == bps_dr)
div_cnt <= 16‘d0;
else
div_cnt <= div_cnt + 1‘d1;
end
else
div_cnt <= 16‘d0;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
bps_clk <= 1‘b0;
else if(div_cnt == 16‘d1)
bps_clk <= 1‘b1;
else
bps_clk <= 1‘b0;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
bps_cnt <= 8‘d0;
else if(rx_done | (bps_cnt == 8‘d12 && (start_bit > 2)))
bps_cnt <= 8‘d0;
else if(bps_clk)
bps_cnt <= bps_cnt + 1‘d1;
else
bps_cnt <= bps_cnt;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
rx_done <= 1‘b0;
else if(bps_cnt == 8‘d159)
rx_done <= 1‘b1;
else
rx_done <= 1‘b0;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_byte <= 8‘d0;
else if(bps_cnt == 8‘d159)
begin
data_byte[0] <= r_data_byte[0][2];
data_byte[1] <= r_data_byte[1][2];
data_byte[2] <= r_data_byte[2][2];
data_byte[3] <= r_data_byte[3][2];
data_byte[4] <= r_data_byte[4][2];
data_byte[5] <= r_data_byte[5][2];
data_byte[6] <= r_data_byte[6][2];
data_byte[7] <= r_data_byte[7][2];
end
else
begin
data_byte[0] <= data_byte[0];
data_byte[1] <= data_byte[1];
data_byte[2] <= data_byte[2];
data_byte[3] <= data_byte[3];
data_byte[4] <= data_byte[4];
data_byte[5] <= data_byte[5];
data_byte[6] <= data_byte[6];
data_byte[7] <= data_byte[7];
end
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
start_bit <= 3‘d0;
r_data_byte[0] <= 8‘d0;
r_data_byte[1] <= 8‘d0;
r_data_byte[2] <= 8‘d0;
r_data_byte[3] <= 8‘d0;
r_data_byte[4] <= 8‘d0;
r_data_byte[5] <= 8‘d0;
r_data_byte[6] <= 8‘d0;
r_data_byte[7] <= 8‘d0;
stop_bit <= 3‘d0;
end
else if(bps_clk)
case(bps_cnt)
0:
begin
start_bit <= 3‘d0;
r_data_byte[0] <= 8‘d0;
r_data_byte[1] <= 8‘d0;
r_data_byte[2] <= 8‘d0;
r_data_byte[3] <= 8‘d0;
r_data_byte[4] <= 8‘d0;
r_data_byte[5] <= 8‘d0;
r_data_byte[6] <= 8‘d0;
r_data_byte[7] <= 8‘d0;
stop_bit <= 3‘d0;
end
5,6,7,8,9,10 : start_bit <= s1_rx + start_bit;
21,22,23,24,25,26 : r_data_byte[0] <= r_data_byte[0] + s1_rx;
37,38,39,40,41,42 : r_data_byte[1] <= r_data_byte[1] + s1_rx;
53,54,55,56,57,58 : r_data_byte[2] <= r_data_byte[2] + s1_rx;
69,70,71,72,73,74 : r_data_byte[3] <= r_data_byte[3] + s1_rx;
85,86,87,88,89,90 : r_data_byte[4] <= r_data_byte[4] + s1_rx;
101,102,103,104,105,106 : r_data_byte[5] <= r_data_byte[5] + s1_rx;
117,118,119,120,121,122 : r_data_byte[6] <= r_data_byte[6] + s1_rx;
133,134,135,136,137,138 : r_data_byte[7] <= r_data_byte[7] + s1_rx;
149,150,151,152,153,154 : stop_bit <= s1_rx + stop_bit;
default :;
endcase
else
begin
r_data_byte[0] <= r_data_byte[0];
r_data_byte[1] <= r_data_byte[1];
r_data_byte[2] <= r_data_byte[2];
r_data_byte[3] <= r_data_byte[3];
r_data_byte[4] <= r_data_byte[4];
r_data_byte[5] <= r_data_byte[5];
r_data_byte[6] <= r_data_byte[6];
r_data_byte[7] <= r_data_byte[7];
end
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
state <= 1‘b0;
else if(nedege)
state <= 1‘b1;
else if(rx_done || (bps_cnt == 8‘d12 && (start_bit > 2)))
state <= 1‘b0;
else
state <= state;
end
endmodule
附：前三次学习下板子的表现
标签：always 一个 output com ase http div 完成 code
原文地址：https://www.cnblogs.com/fpgamzy/p/10355473.html
