标签：app 技术 高斯分布 final slot for 偏差 targe remove
Timing sign-off Corner = library PVT +RC Corner + OCV
针对每个工艺结点，foundry都会给出一张类似的timing sign-off表格，定义了所有需要做timing sign-off的corner（实际需要sign-off的corner还需要乘以工作模式，对于STA，不同的工作模式，用不同的SDC文件予以区别）
uncertainty=clock jitter + Xps setup/hold margin + DPT，其中clock jitter由用户根据所用PLL的精度来确定；Xps由foundry提供，如：30ps for setup, 40ps for hold; DPT一项表示需要加的额外margin用于cover mask misalignment引起的偏差，该值亦由foundary提供，比如5ps for setup, 3ps for hold。
世界上没有两片相同的叶子，半导体世界里没有两只相同的管子。library中的cell delay是在某个固定的PVT（operating condition）下仿真得出的，也就是下图中的Nominal delay，而实际上在芯片内部由于工艺偏差、电压降、温度变化，cell的delay并不是一个固定值，而是一个随机值，遵循高斯分布或门特卡洛分布。
在STA中用OCV来模拟这一『特征』，OCV全称on chip variation，用于描述不同管子间由于工艺偏差、电压降、温度变化引起的delay变化，也用于描述工艺偏差引起的net厚度宽度的变化从而导致net的电容电阻变化。
PVT跟OCV都是用于描述Process、Voltage、Temperature对timing的影响，两者有何区别？
PVT：主要取决于外部因素，在某一固定的工艺点、芯片的工作电压、周围环境温度对芯片性能的影响。更直白的理解：同一颗芯片在不同工作电压、环境温度下的性能表现。
OCV：用于模拟芯片内部不同管子由于工艺偏差、电压降、温度变化引起的性能变化，这种变化更宏观的表现是：不同芯片在相同PVT下的性能表现不同。
在timing sign-off时，为什么要在Nominal delay上加OCV？
因为Nominal delay是在固定PVT下仿真得出的delay，而实际上由于OCV的影响，管子的delay是呈高斯分布或门特卡洛分布，要想保证yield，就必须在timing sign-off时将OCV考虑在内，以保证大部分管子都可以满足时序要求。对每一代工艺，foundry都会做大量测试，针对每个corner找到一组适合的OCV值，这组值可以保证足够高的yield，而如果进一步加紧这个值，并不会更有效的提高yield。在SOCV/POCV里的多少sigma(如：3-sigma)的选取也是出于相同的考虑
Interconnect variation: Another area of on-chip variation is in interconnect height and width, resulting in variation in both resistance and capacitance. Because the delay from interconnect is becoming more dominant as geometries shrink, you should pay attention to accurate modeling of interconnect variations. Two potential sources of this variation are the CMP (chemical-mechanical-planarization) process and the proximity effects in the photolithography and etch processes. Variation in the CMP process results from the difference in hardness between the interconnect material and the dielectric. Ideally, after the designer has etched trenches into the dielectric below an interconnect layer and copper on the wafer, the CMP process removes the unwanted copper, leaving only lines and vias. The copper line is softer than the dielectric material, resulting in "dishing" and erosion, which cause uneven removal of the copper and dielectric. Dishing is a function of line width and density, and erosion is a function of line space and density. Another source of variation in thickness due to CMP is a morerandom variation resulting in a gradient across the wafer. You can see thisgradient in die-to-die variations and even across-die variations for large die.You would ideally model this random, nondeterministic variation statistically.However, if you can obtain process data to model this variation, then you canmodel it deterministically as a function of position on the wafer. In thisscenario, you give an adder or subtracter, depending on the x,y position on thedie, to the RC value. Etch-proximity effects appear as "microloading," whichmeans that the etch process overetches isolated lines. A dual-damascenestructure uses only a single metal-deposition step to simultaneously form themain metal lines and the metal in the vias. That is, the formation of both thetrenches and the vias occurs in one dielectric layer. Overetching results in awider trench and, hence, a wider metal line. Photolithographic effects also cause problems. Diffraction andlocal scattering in photolithography may overexpose densely spaced lines andunderexpose isolated lines. Tiling and metal slotting reduce the variation infeature density and mitigate these effects. Tiling algorithms give differentresults, but a general rule states that a less dense gradient yields smallerline-width variations on the die. Tiling does have its drawbacks, however. Asone of the last integration steps in an SOC-design flow, tiling involvescalculations that the extractor performs using density parameters. Thesecalculations can result in different RC values before and after tiling. Tilingcan also result in small additional delay effects on timing. The final designmay not meet the desired target frequency once you account for tiling. Whetherit does depends largely on the design and the methods you use to meet thetiling requirements.
方法学上概念清晰了之后，EDA工具端的操作就十分简单了，在EDA工具中如何设置OCV？每家工具都有各自不同的命令/变量控制，跟OCV相关的大致可分为四部分，此处以Tempus的命令为例：
全局控制：set_analysis_mode -analysisType onChipVariation
设置OCV：set_timing_derate -cell_delay/net_delay/cell_check -late/early -data/clock (1-d%)；其中d%是foundry在sign-off表格中给出的OCV值
Report OCV: report_statistical_timing_derate_factors
Debug timing时在timing report中将derate列显示出来：set_global report_timing_format {instance arc delay slew arrival user_derate}
由于工艺的进步，flat OCV在先进工艺如16，7中已经逐步被AOCV, SOCV/POCV取代，以剔除悲观度。
标签：app 技术 高斯分布 final slot for 偏差 targe remove
原文地址：https://www.cnblogs.com/lelin/p/11391998.html
