标签：开关 ec2 ilo 建模 mos color rpm verilog mod
VerilogHDL内建基元门：
多输入门：and, nand, or, nor, xor, xnor;
多输出门：buf, not
三态门：bufif0, bufif1, notif0, notif1;
上拉、下拉门：pullup, pulldown;
MOS开关：cmos, nmos, pmos, rcmos, rnmos, rpmmos;
双向开关：tran, tranif0, tranif1, rtran, rtranif0, rtranif1;
示例1：2-4译码器
module dec24(a,b,en,dataout); input a, b, en; output [0:3]dataout; wire abar, bbar; not #(1,2) u0(abar, a); u1(bbar, b); nand #(4,3) s0(dataout[0],en,abar,bbar), s1(dataout[1],en,abar,b), s2(dataout[2],en,a,bbar), s3(dataout[3],en,a,b); endmodule
示例2：主从触发器
module d_flipflop(d, clk, q, qbar); input d, clk; output q, qbar; not n0(not_d, d), n1(not_clk, clk), n3(not_y, y); nand x1(d1,d,clk), x2(d2,clk,not_d), x3(y,d1,ybar), x4(ybar,y,d2), x5(y1,y,not_clk), x6(y2,not_y,not_clk), x7(q,qbar,y1), x8(qbar,y2,q); endmodule
标签：开关 ec2 ilo 建模 mos color rpm verilog mod
原文地址：https://www.cnblogs.com/vilicute/p/11595155.html
