标签：计数 efault splay nbsp end class modelsim 实现 tput
硬件平台：DE2-115
软件环境：Quartus II 15.1
采样了较为简单的计数方法，详细代码就不讲解了，分为三个模块，一个是计数模块 count.v，一个是显示模块 disp.v，还有一个是顶层模块 miaobiao.v。有清零按键和暂停拨码开关。
顶层模块：
1 module miaobiao( 2 clk, 3 rst_n, 4 pause, 5 6 Hex0, 7 Hex1, 8 Hex2, 9 Hex3, 10 Hex4, 11 Hex5, 12 ); 13 14 input clk; 15 input rst_n; 16 input pause; 17 18 output[6:0] Hex0; 19 output[6:0] Hex1; 20 output[6:0] Hex2; 21 output[6:0] Hex3; 22 output[6:0] Hex4; 23 output[6:0] Hex5; 24 25 wire[3:0]h_sec_h; 26 wire[3:0]h_sec_l; 27 28 wire[3:0]sec_h; 29 wire[3:0]sec_l; 30 31 wire[3:0]fen_h; 32 wire[3:0]fen_l; 33 34 count u0( 35 .clk(clk), 36 .rst_n(rst_n), 37 .pause(pause), 38 39 .h_sec_h(h_sec_h), 40 .h_sec_l(h_sec_l), 41 42 .sec_h(sec_h), 43 .sec_l(sec_l), 44 45 .fen_h(fen_h), 46 .fen_l(fen_l) 47 ); 48 49 disp u1( 50 51 .h_sec_l(h_sec_l), 52 .h_sec_h(h_sec_h), 53 54 .sec_l(sec_l), 55 .sec_h(sec_h), 56 57 .fen_l(fen_l), 58 .fen_h(fen_h), 59 60 .Hex0(Hex0), 61 .Hex1(Hex1), 62 .Hex2(Hex2), 63 .Hex3(Hex3), 64 .Hex4(Hex4), 65 .Hex5(Hex5) 66 ); 67 68 endmodule
计数模块：
1 module count( 2 clk, 3 rst_n, 4 pause, 5 6 h_sec_h, 7 h_sec_l, 8 9 sec_h, 10 sec_l, 11 12 fen_h, 13 fen_l 14 ); 15 16 input clk; 17 input rst_n; 18 input pause; //pause为0时正常计数，为1时暂停计数 19 20 output reg[3:0] h_sec_h; //百分秒低位 21 output reg[3:0] h_sec_l; //百分秒高位 22 23 output reg[3:0] sec_h; //秒高位 24 output reg[3:0] sec_l; //秒低位 25 26 output reg[3:0] fen_h; //分低位 27 output reg[3:0] fen_l; //分高位 28 29 reg flag1; //flag1为百分秒向秒的进位 30 reg flag2; //flag2为秒向分的进位 31 reg[27:0] cnt; // 32 reg clk_100hz; 33 34 /* 100hz 分频 */ 35 always@(posedge clk or negedge rst_n) 36 if(!rst_n) 37 cnt <= 28‘d0; 38 else if(cnt == 249999) 39 cnt <= 28‘d0; 40 else 41 cnt <= cnt + 1‘b1; 42 43 always@(posedge clk or negedge rst_n) 44 if(!rst_n) 45 clk_100hz <= 1‘b0; 46 else if(cnt == 249999) 47 clk_100hz <= !clk_100hz; 48 else 49 clk_100hz <= clk_100hz; 50 51 /* 百分秒计数进程，每计满100，flag1产生一个进位 */ 52 always@(posedge clk_100hz or negedge rst_n) 53 begin 54 if(!rst_n) begin 55 {h_sec_h,h_sec_l} <= 8‘h00; 56 flag1 <= 1‘b0; 57 end 58 else if(!pause) begin 59 if(h_sec_l == 9) begin 60 h_sec_l <= 4‘d0; 61 if(h_sec_h == 9) begin 62 h_sec_h <= 4‘d0; 63 flag1 <= 1‘b1; 64 end 65 else 66 h_sec_h <= h_sec_h + 1‘b1; 67 end 68 else begin 69 h_sec_l <= h_sec_l + 1‘b1; 70 flag1 <= 1‘b0; 71 end 72 end 73 end 74 75 /* 秒计数进程，每计满60，flag2产生一个进位 */ 76 always@(posedge flag1 or negedge rst_n) 77 begin 78 if(!rst_n) begin 79 {sec_h,sec_l} <= 8‘h00; 80 flag2 <= 0; 81 end 82 else if(sec_l == 9) begin 83 sec_l <= 4‘d0; 84 if(sec_h == 5) begin 85 sec_h <= 4‘d0; 86 flag2 <= 1‘b1; 87 end 88 else 89 sec_h <= sec_h + 1‘b1; 90 end 91 else begin 92 sec_l <= sec_l + 1‘b1; 93 flag2 <= 1‘b0; 94 end 95 end 96 97 /* 分计数进程，每计数满60，系统自动清零 */ 98 always@(posedge flag2 or negedge rst_n) 99 begin 100 if(!rst_n) begin 101 {fen_h,fen_l} <= 8‘h00; 102 end 103 else if(fen_l == 9) begin 104 fen_l <= 4‘d0; 105 if(fen_h == 5) 106 fen_h <= 4‘d0; 107 else 108 fen_h <= fen_h + 1‘b1; 109 end 110 else 111 fen_l <= fen_l + 1‘b1; 112 end 113 endmodule 114 115 116 117 118
显示模块：
1 module disp( 2 3 h_sec_l, 4 h_sec_h, 5 6 sec_l, 7 sec_h, 8 9 fen_l, 10 fen_h, 11 12 Hex0, 13 Hex1, 14 Hex2, 15 Hex3, 16 Hex4, 17 Hex5, 18 ); 19 20 input[3:0] h_sec_h; 21 input[3:0] h_sec_l; 22 23 input[3:0] sec_h; 24 input[3:0] sec_l; 25 26 input[3:0] fen_h; 27 input[3:0] fen_l; 28 29 output reg[6:0] Hex0; 30 output reg[6:0] Hex1; 31 output reg[6:0] Hex2; 32 output reg[6:0] Hex3; 33 output reg[6:0] Hex4; 34 output reg[6:0] Hex5; 35 36 always@(*) //百分秒个位控制 37 begin 38 case(h_sec_l) 39 0:Hex0 <= 7‘b1000000; //0 40 1:Hex0 <= 7‘b1111001; //1 41 2:Hex0 <= 7‘b0100100; //2 42 3:Hex0 <= 7‘b0110000; //3 43 4:Hex0 <= 7‘b0011001; //4 44 5:Hex0 <= 7‘b0010010; //5 45 6:Hex0 <= 7‘b0000010; //6 46 7:Hex0 <= 7‘b1111000; //7 47 8:Hex0 <= 7‘b0000000; //8 48 9:Hex0 <= 7‘b0010000; //9 49 default:Hex0 <= 7‘b1000000; //0 50 endcase 51 end 52 53 always@(*) //百分秒十位控制 54 begin 55 case(h_sec_h) 56 0:Hex1 <= 7‘b1000000; //0 57 1:Hex1 <= 7‘b1111001; //1 58 2:Hex1 <= 7‘b0100100; //2 59 3:Hex1 <= 7‘b0110000; //3 60 4:Hex1 <= 7‘b0011001; //4 61 5:Hex1 <= 7‘b0010010; //5 62 6:Hex1 <= 7‘b0000010; //6 63 7:Hex1 <= 7‘b1111000; //7 64 8:Hex1 <= 7‘b0000000; //8 65 9:Hex1 <= 7‘b0010000; //9 66 default:Hex1 <= 7‘b1000000; //0 67 endcase 68 end 69 70 always@(*) // 71 begin 72 case(sec_l) 73 0:Hex2 <= 7‘b1000000; //0 74 1:Hex2 <= 7‘b1111001; //1 75 2:Hex2 <= 7‘b0100100; //2 76 3:Hex2 <= 7‘b0110000; //3 77 4:Hex2 <= 7‘b0011001; //4 78 5:Hex2 <= 7‘b0010010; //5 79 6:Hex2 <= 7‘b0000010; //6 80 7:Hex2 <= 7‘b1111000; //7 81 8:Hex2 <= 7‘b0000000; //8 82 9:Hex2 <= 7‘b0010000; //9 83 default:Hex2 <= 7‘b1000000; //0 84 endcase 85 end 86 87 always@(*) // 88 begin 89 case(sec_h) 90 0:Hex3 <= 7‘b1000000; //0 91 1:Hex3 <= 7‘b1111001; //1 92 2:Hex3 <= 7‘b0100100; //2 93 3:Hex3 <= 7‘b0110000; //3 94 4:Hex3 <= 7‘b0011001; //4 95 5:Hex3 <= 7‘b0010010; //5 96 default:Hex3 <= 7‘b1000000; //0 97 endcase 98 end 99 100 always@(*) // 101 begin 102 case(fen_l) 103 0:Hex4 <= 7‘b1000000; //0 104 1:Hex4 <= 7‘b1111001; //1 105 2:Hex4 <= 7‘b0100100; //2 106 3:Hex4 <= 7‘b0110000; //3 107 4:Hex4 <= 7‘b0011001; //4 108 5:Hex4 <= 7‘b0010010; //5 109 6:Hex4 <= 7‘b0000010; //6 110 7:Hex4 <= 7‘b1111000; //7 111 8:Hex4 <= 7‘b0000000; //8 112 9:Hex4 <= 7‘b0010000; //9 113 default:Hex4 <= 7‘b1000000; //0 114 endcase 115 end 116 117 always@(*) // 118 begin 119 case(fen_h) 120 0:Hex5 <= 7‘b1000000; //0 121 1:Hex5 <= 7‘b1111001; //1 122 2:Hex5 <= 7‘b0100100; //2 123 3:Hex5 <= 7‘b0110000; //3 124 4:Hex5 <= 7‘b0011001; //4 125 5:Hex5 <= 7‘b0010010; //5 126 default:Hex5 <= 7‘b1000000; //0 127 endcase 128 end 129 130 endmodule
仿真用的是Modelsim SE-64 10.4，只对计数模块进行了仿真，不是很直观，代码如下：
1 `timescale 1ns/1ns 2 `define clk_period 20 3 module count_tb; 4 reg clk; 5 reg rst_n; 6 reg pause; 7 wire[3:0] h_sec_h; 8 wire[3:0] h_sec_l; 9 wire[3:0] sec_l; 10 wire[3:0] sec_h; 11 wire[3:0] fen_h; 12 wire[3:0] fen_l; 13 count u0( 14 .clk(clk), 15 .rst_n(rst_n), 16 .pause(pause), 17 .h_sec_h(h_sec_h), 18 .h_sec_l(h_sec_l), 19 .sec_h(sec_h), 20 .sec_l(sec_l), 21 .fen_h(fen_h), 22 .fen_l(fen_l) 23 ); 24 25 initial 26 clk = 0; 27 always#(`clk_period/2) clk = ~clk; 28 29 initial 30 begin 31 rst_n = 1‘b0; 32 #(`clk_period); 33 rst_n = 1‘b1; 34 pause = 1‘b1; 35 #(`clk_period*5); 36 pause = 1‘b0; 37 #(`clk_period*1000000); 38 $stop; 39 end 40 endmodule
由于分频为100hz进行百分秒计数，Modelsim跑的比较慢，所以我将百分秒计数模块，秒计数模块，分计数模块一个个单独来进行仿真，这样速度较快，容易找到问题，功能上是可以完全实现的。
标签：计数 efault splay nbsp end class modelsim 实现 tput
原文地址：https://www.cnblogs.com/571328401-/p/11626094.html
