SPI Protocol - 维基百科

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Standards[edit]

The SPI bus is a de facto standard. However, the lack of a formal standard is reflected in a wide variety of protocol options. Different word sizes are common. Every device defines its own protocol, including whether it supports commands at all. Some devices are transmit-only; others are receive-only. Chip selects are sometimes active-high rather than active-low. Some protocols send the least significant bit first.

翻译：SPI总线协议，是一个约定俗成的“标准”。由于没有正式官方而详细的标准细则，实际应用出出现了多种多样的协议配置。（可以这样理解，SPI协议太简洁了，在其上层协议上没有做明确规定，所以用法多样，这种现象类似于，CAN总线协议与CAN OPEN/基于CAN的J1939协议）。这种多样性在于，传输数据的长度不固定、是否支持命令可选、可以只发不收或者只收、发送bits流数据的顺序（LSB/MSB）。

【感想】非正式地说，SPI类似于MCU/SoC内部的寄存器传输，或者数字电路中的移位寄存器，就是为了高速和高效地交换数据，稍微区别在SPI用在芯片之间。

Advantages[edit] 优点

• 1. Full duplex communication in the default version of this protocol 全双工通信
• 2. Push-pull drivers (as opposed to open drain) provide good signal integrity and high speed
• 3. Higher throughput than I²C or SMBus. Not limited to any maximum clock speed, enabling potentially high speed 
• 3. 比I2C和SMBus协议更高的传输速率。传输速率无上限，能够高速传输
4. Complete protocol flexibility for the bits transferred 拥有完美的传输弹性
• Not limited to 8-bit words 不限8bits words传输
• Arbitrary choice of message size, content, and purpose
• Extremely simple hardware interfacing 硬件接口极致地简洁
  • Typically lower power requirements than I²C or SMBus due to less circuitry (including pull up resistors)
  • No arbitration or associated failure modes - unlike CAN-bus
  • Slaves use the master‘s clock and do not need precision oscillators
  • Slaves do not need a unique address – unlike I²C or GPIB or SCSI
  • Transceivers are not needed - unlike CAN-bus
• Uses only four pins on IC packages, and wires in board layouts or connectors, much fewer than parallel interfaces
• At most one unique bus signal per device (chip select); all others are shared
• Signals are unidirectional allowing for easy galvanic isolation
• Simple software implementation

Clock polarity and phase[edit] 时钟极性和相位

 

A timing diagram showing clock polarity and phase. Red lines denote clock leading edges, and blue lines, trailing edges.

In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Motorola SPI Block Guide^[2] names these two options as CPOL and CPHA (for clock "pol"arity and "pha"se) respectively, a convention most vendors have also adopted.

The timing diagram is shown to the right. The timing is further described below and applies to both the master and the slave device.

• CPOL determines the polarity of the clock. The polarities can be converted with a simple inverter.
  • CPOL=0 is a clock which idles at 0, and each cycle consists of a pulse of 1. That is, the leading edge is a rising edge, and the trailing edge is a falling edge.
  • CPOL=1 is a clock which idles at 1, and each cycle consists of a pulse of 0. That is, the leading edge is a falling edge, and the trailing edge is a rising edge.
• CPHA determines the timing (i.e. phase) of the data bits relative to the clock pulses. Conversion between these two forms is non-trivial.
  • For CPHA=0, the "out" side changes the data on the trailing edge of the preceding clock cycle, while the "in" side captures the data on (or shortly after) the leading edge of the clock cycle. The out side holds the data valid until the trailing edge of the current clock cycle. For the first cycle, the first bit must be on the MOSI line before the leading clock edge.
  • An alternative way of considering it is to say that a CPHA=0 cycle consists of a half cycle with the clock idle, followed by a half cycle with the clock asserted.
  • For CPHA=1, the "out" side changes the data on the leading edge of the current clock cycle, while the "in" side captures the data on (or shortly after) the trailing edge of the clock cycle. The out side holds the data valid until the leading edge of the following clock cycle. For the last cycle, the slave holds the MISO line valid until slave select is deasserted.
  • An alternative way of considering it is to say that a CPHA=1 cycle consists of a half cycle with the clock asserted, followed by a half cycle with the clock idle.

The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle.

This adds more flexibility to the communication channel between the master and slave.

SPI Protocol - 维基百科

标签：change   style   potential   eve   命令   ase   reflect   enc   define   

原文地址：https://www.cnblogs.com/mapleay/p/11663973.html