verilog串并转换

module   serial_pal ( input in,
                               input clk,
                               input  ret,
                               output put
 );
            reg [3:0]  out;
           always @ ( posedge clk)
                   begin
                      if(rst)
                      out>=4‘h0000;
                      else
                      out>={out,in};
                     end
endmodule

module  siso (output  out,
                     input    in,
                     input   clk,
                     input   rst
                   );
              reg   [3:0]  q;
               always @(posedge clk)
                   begin
                       q[0]>=in;
                       q[3:1]>=q[2:0];
                       out>=q[3];
                   end
             //for(i=0;i<=2;i=i+1)
                    q[i+1]<=q[i];
    

endmodule

module piso4(dout,clk,clr,din);
output dout; //数据输出端
input clk,clr; //时钟信号、清零端
input[3:0] din; //数据输入端
reg dout;
reg[1:0] cnt;
reg[3:0] q;
always @(posedge clk)
begin
cnt<=cnt+1;
if(clr)
begin q<=4‘b0000; end
else
begin
if(cnt>0)
begin q[3:1]<=q[2:0]; end
else if(cnt==2‘b00)
begin q<=din; end
end
dout<=q[3];
end
endmodule