标签:输出 input tput 部分 开关 重置 verilog 定义 控制器
模块具有三个输入:时钟,重置,和汽车状态、以及六个输出分别控制左右(l,r)三色LED的红绿蓝三个阴极
module ? car_rear_light
(??? input ?clk,
???? input ?rst,
???? input ?[ 3 : 0 ]car_status,
???? output ? reg [ 0 : 0 ]l_light_r,??????? //左侧红灯
???? output ? reg [ 0 : 0 ]r_light_r,??????? //右侧红灯
???? output ? reg [ 0 : 0 ]l_light_g,??????? //左侧绿灯
???? output ? reg [ 0 : 0 ]r_light_g,??????? //右侧绿灯?
???? output ? reg [ 0 : 0 ]l_light_b,??????? //左侧蓝灯
???? output ? reg [ 0 : 0 ]r_light_b???????? //右侧蓝灯
);
因为左右转向灯和双闪均为黄色,所以将左右两个三色LED的红、绿阴极统一安排给l_light、r_light两个变量控制
红+绿 <= 污黄
reg [ 0 : 0 ]l_light;
reg [ 0 : 0 ]r_light;
always @( posedge ?clk)
begin
????l_light_r? = ?l_light;
????l_light_g? = ?l_light;
????r_light_r? = ?r_light;
????r_light_g? = ?r_light;
end
分频模块重新定义参数,分频系数为12M,将板载12MHz的晶振分为1Hz的时钟。
wire ?clk_1Hz;
divide ??#(.WIDTH( 32 ),.N( 12_000_000 ))?? u1 ?(?????? //分频12MHz到1Hz
????.clk????(clk),
????.rst_n??(rst),
????.clkout?(clk_1Hz)???
);
汽车状态由拨码开关控制:
0001 —— 直行,不闪灯
0010 —— 左转,闪左灯
0100 —— 右转,闪右灯
1000 —— 故障,双闪
1111 —— 倒车,两灯白色常亮
always @( posedge ?clk_1Hz)
begin
???? case (car_status)
???????? 4'b0001 :???????????????????????????????? //直行
???????? begin
????????????l_light? <= ? 1 ;
????????????r_light? <= ? 1 ;
????????????l_light_b? <= ? 1 ;
????????????r_light_b? <= ? 1 ;
???????? end
???????? 4'b0010 :???????????????????????????????? //左转
???????? begin
????????????l_light? <= ? ~ l_light;
????????????r_light? <= ? 1 ;
????????????l_light_b? <= ? 1 ;
????????????r_light_b? <= ? 1 ;
???????? end
???????? 4'b0100 :???????????????????????????????? //右转
???????? begin
????????????l_light? <= ? 1 ;
????????????r_light? <= ? ~ r_light;
????????????l_light_b? <= ? 1 ;
????????????r_light_b? <= ? 1 ;
???????? end
???????? 4'b1000 :???????????????????????????????? //双闪
???????? begin
????????????l_light? <= ? ~ l_light;
????????????r_light? <= ? ~ r_light;
????????????l_light_b? <= ? 1 ;
????????????r_light_b? <= ? 1 ;
???????? end
?????????? 4'b1111 :?????????????????????????????? //倒车
?????????? begin
????????????l_light? <= ? 0 ;
????????????r_light? <= ? 0 ;
????????????l_light_b? <= ? 0 ;
????????????r_light_b? <= ? 0 ;
?????????? end
???????? default :
???????? begin
????????????l_light? <= ? 1 ;
????????????r_light? <= ? 1 ;
????????????l_light_b? <= ? 1 ;
????????????r_light_b? <= ? 1 ;
????????????????
???????? end
???? endcase
end
标签:输出 input tput 部分 开关 重置 verilog 定义 控制器
原文地址:https://www.cnblogs.com/codaland/p/11965649.html