移位寄存器及verilog代码

//通用移位寄存器
module Universal_Shift_Reg#(parameter word_size = 8)(
    output  reg[word_size-1:0]      Data_out,
    output                          MSB_out, LSB_out,
    input      [word_size-1:0]      Data_in,
    input                           MSB_in, LSB_in,
    input                           s0, s1, clk, rst
);
    assign  MSB_out = Data_out[word_size-1];
    assign  LSB_out = Data_out[0];
    
    always @(posedge clk)
        begin
            if(rst==1‘b1)   Data_out <= 0;
            else 
                case({s1, s0})
                    0:  Data_out <= Data_out;                           //maintain
                    1:  Data_out <= {MSB_in, Data_out[word_size-1:1]};  //MSB shift
                    2:  Data_out <= {Data_out[word_size-2:0], LSB_in};  //LSB shift
                    3:  Data_out <= Data_in;                            //parallel input
                endcase
            
        end
endmodule

module shift_reg#(parameter word_size = 4)(
    output                      reg_out,
    input                       clk, rst,reg_in
);
    reg     [word_size-1:0]     reg_data;

    assign  reg_out = reg_data[0];
    always @(posedge clk, negedge rst)
        if(!rst)    reg_data <= {word_size{1‘b0}};                  //nonblock assignment
        else        reg_data <= {reg_in, reg_data[word_size-1:1]};
endmodule

module barrel_reg #(parameter word_size = 8)(
    output reg      [word_size-1:0]     data_out,
    input           [word_size-1:0]     data_in,
    input                               load, clk, rst
);

    always @(posedge clk, posedge rst)
        begin
            if(rst) data_out <= {word_size{1‘b0}};
            else if(load)   data_out <= {data_in[word_size-2:0], data_in[word_size-1]};
        end
endmodule