Vivado Non-Project Flow

 1 # -----------------------------------------------------------------------------
 2 # Vivado Non-Project Flow
 3 # -----------------------------------------------------------------------------
 4 set DESIGN "top"
 5 
 6 # -----------------------------------------------------------------------------
 7 config_webtalk -user off
 8 
 9 # -----------------------------------------------------------------------------
10 proc read_filelist {filelist} {
11     global hdl_list
12     global incdir_list
13     set fp [open $filelist r]
14     while {[gets $fp fname] != -1} {
15         if {[regexp {^//} $fname]} {
16             continue
17         } elseif {[regexp {^\S+\.v} $fname]} {
18             lappend hdl_list $fname
19         } elseif {[regexp {^-v} $fname]} {
20             regsub {^-v} $fname "" $fname_sub
21             lappend hdl_list $fname_sub
22         } elseif {[regexp {^\+incdir\+} $fname]} {
23             regsub {^\+incdir\+} $fname "" $fname_sub
24             lappend incdir_list $fname_sub
25         }
26     }
27     close $fp
28 }
29 
30 # -----------------------------------------------------------------------------
31 read_filelist "../rtl/filelist.f"
32 
33 set_property verilog_define "SYNTHESIS" [current_fileset]
34 set_property include_dirs $incdir_list [current_fileset]
35 set_property top ${DESIGN} [current_fileset]
36 
37 read_verilog -library work $hdl_list
38 read_ip "../rtl/ip/ila_debug.xci"
39 read_xdc "../scr/${DESIGN}.xdc"
40 
41 # -----------------------------------------------------------------------------
42 synth_design -top ${DESIGN} -part xc7z020clg400-2
43 write_checkpoint -force ${DESIGN}_synth.dcp
44 report_utilization -file ${DESIGN}_synth_utilization.rpt
45 report_timing_summary -file ${DESIGN}_synth_timing_summary.rpt
46 
47 # -----------------------------------------------------------------------------
48 if {[llength [get_debug_cores -quiet]] > 0} {
49     implement_debug_core
50 }
51 
52 # -----------------------------------------------------------------------------
53 opt_design -directive Explore
54 place_design -directive Explore
55 phys_opt_design -directive Explore
56 write_checkpoint -force ${DESIGN}_placed.dcp
57 report_utilization -file ${DESIGN}_placed_utilization.rpt
58 report_timing_summary -file ${DESIGN}_placed_timing_summary.rpt
59 
60 # -----------------------------------------------------------------------------
61 route_design -directive Explore -tns_cleanup
62 phys_opt_design -directive Explore
63 write_checkpoint -force ${DESIGN}_routed.dcp
64 report_route_status -file ${DESIGN}_routed_status.rpt
65 report_timing_summary -file ${DESIGN}_routed_timing_summary.rpt
66 
67 # -----------------------------------------------------------------------------
68 write_bitstream -force ${DESIGN}.bit
69 write_cfgmem -format bin -interface SPIx1 -size 256 -loadbit "up 0 ${DESIGN}.bit" ${DESIGN}.bin
70 write_debug_probes ${DESIGN}.ltx