verilog behavioral modeling--procedural continous assignment(不用)

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assign / deassgin

force /release

the procedural continuous assignments(using keywords assign and force) are procedural statements that allow expressions to be driven continously onto variables or nets.

1. net_lvalue = expression  in force statement net_lvalue is verialbe reference or a net reference .  can be a concatenation of any of the above .bit-selects and part-selects of vector variables are not allowed

   variable_lvalue = expression   in assign statement  variable_lvalue is  verialbe reference or a concatenation of variables , not be a memory word(array reference) or a bit-select or a part-select of a variable

2.assign variable_assignment

   deassign variable_lvalue

   force variable_assignment

   force net_assignment

   release variable_lvalue

   release net_lvalue

3.the assign and deassign procedural statements

   the assign procedural continuous assignment statement shall override all procedural assignments to a variable(过程性持续赋值优先级要高于一般的过程赋值)

   the deassign procedural statement shall end a procedural continous assignment to a variable.

  the value of the variable shall remain the same until the variable is assigned a new value through a procedural assignment or procedural continuous assignment.

  If the keyword assign is applied to a variable for which there is already a procedural continous assignment,then this new procedural continous assignment shall deassgin the variable before making the new procedural continuous assignment.(如果有assign 先deassign, 再assign)

4.the force and release procedural statements

  1.these statements have a similar effect to the assign-deassign pair,but a force can be applied to nets as well as to variables.

  2. the left-hand side of the assignment can be a variable, a net ,a constant bit-select of a vector net, a part-select of a vector net , or a concatentation. It cannot be a memory word(array reference) a bit-select or

        a part-select of a vector variable.(看来force 使用的范围要比assign大，还是尽量用force-release好些)

  3.a force  statement to a variable shall override a procedural assignment or an assign procedural continous assignment to the variable until a release procedural statement is executed on the variable.

  4.when released, shall not immediately change value.the variable shall maintain its current value until the next procedural assignment or procedural continuous assignment to the variable.

  5. releasing a variable that currently has an active assign procedural continous assignment shall immediately reestablish that assignment.

   6.A force procedural statement on a net shall override all drivers of the net --gate outputs,module outputs,and continous assignments--until a release procedural statement is executed on the net.when released,

the net shall immediately be assgined the value determined by the dirvers of the net.

verilog behavioral modeling--procedural continous assignment(不用)

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原文地址：http://www.cnblogs.com/chip/p/4074016.html