FPGA——TLV5618 Driver(未完成)

  1 module tlv5618(
  2     clk         ,//50MHz时钟
  3     rst_n       ,//复位
  4     dac_data    ,//16位数据输入
  5     start       ,//DAC驱动使能
  6     set_done    ,//数据转换完成标志位
  7 
  8     dac_cs_n    ,//片选
  9     dac_din     ,//16数据串行输出
 10     dac_sclk    ,//DAC芯片时钟
 11     dac_state    //开始发送状态标志位
 12     );
 13 
 14     //参数定义
 15     parameter           DATA_W =           16;
 16     parameter           SCLC_W =            6;
 17 
 18     //输入信号定义
 19     input               clk         ;
 20     input               rst_n       ;
 21     input [DATA_W-1:0]  dac_data    ;
 22     input               start       ;
 23 
 24     //输出信号定义
 25     output              dac_cs_n    ;
 26     output              dac_din     ;
 27     output              dac_sclk    ;
 28     output              dac_state   ;
 29     output              set_done    ;
 30 
 31     //输出信号定义
 32     reg                 dac_cs_n    ;
 33     reg                 dac_din     ;
 34     reg                 dac_sclk    ;
 35     wire                dac_state   ;
 36     reg                    set_done    ;
 37 
 38     //中间信号定义
 39     reg                 div_cnt     ;
 40     reg                 en          ;
 41     reg   [SCLC_W-1:0]  scl_cnt     ;
 42     wire                add_div_cnt    ;
 43     wire                end_div_cnt    ;
 44     wire                add_scl_cnt    ;
 45     wire                end_scl_cnt    ;     
 46 
 47     //SCLK分频器，40ns
 48     always @(posedge clk or negedge rst_n)begin
 49         if(!rst_n)begin
 50             div_cnt <= 0;
 51         end
 52         else if(add_div_cnt)begin
 53             if(end_div_cnt)
 54                 div_cnt <= 0;
 55             else
 56                 div_cnt <= div_cnt + 1‘b1;
 57             end
 58     end
 59     assign add_div_cnt = (en == 1);
 60     assign end_div_cnt = add_div_cnt && div_cnt == 2-1 ;
 61 
 62     always @(posedge clk or negedge rst_n)begin
 63         if(!rst_n)begin
 64             scl_cnt <= 0;
 65         end
 66         else if(add_scl_cnt)begin
 67             if(end_scl_cnt)
 68                 scl_cnt <= 0;
 69             else
 70                 scl_cnt <= scl_cnt + 1‘b1;
 71             end
 72     end
 73     assign add_scl_cnt = (end_div_cnt == 1);
 74     assign end_scl_cnt = add_scl_cnt && scl_cnt == 34-1;
 75 
 76     always@(posedge clk or negedge rst_n)begin
 77         if(rst_n==1‘b0)begin
 78             dac_cs_n <= 1‘b1;
 79             dac_din  <= 1‘b1;
 80             dac_sclk <= 1‘b0;
 81         end
 82         else if(en) begin
 83             case (scl_cnt)
 84                 0 : begin
 85                     dac_cs_n <= 1‘b0;
 86                     dac_din  <= dac_data[15];
 87                     dac_sclk <= 1‘b1;
 88                 end
 89                 2 : begin dac_din <= dac_data[14];dac_sclk <= 1‘b1;end
 90                 4 : begin dac_din <= dac_data[13];dac_sclk <= 1‘b1;end
 91                 6 : begin dac_din <= dac_data[12];dac_sclk <= 1‘b1;end
 92                 8 : begin dac_din <= dac_data[11];dac_sclk <= 1‘b1;end
 93                 10: begin dac_din <= dac_data[10];dac_sclk <= 1‘b1;end
 94                 12: begin dac_din <= dac_data[9] ;dac_sclk <= 1‘b1;end
 95                 14: begin dac_din <= dac_data[8] ;dac_sclk <= 1‘b1;end
 96                 16: begin dac_din <= dac_data[7] ;dac_sclk <= 1‘b1;end
 97                 18: begin dac_din <= dac_data[6] ;dac_sclk <= 1‘b1;end
 98                 20: begin dac_din <= dac_data[5] ;dac_sclk <= 1‘b1;end
 99                 22: begin dac_din <= dac_data[4] ;dac_sclk <= 1‘b1;end
100                 24: begin dac_din <= dac_data[3] ;dac_sclk <= 1‘b1;end
101                 26: begin dac_din <= dac_data[2] ;dac_sclk <= 1‘b1;end
102                 28: begin dac_din <= dac_data[1] ;dac_sclk <= 1‘b1;end
103                 30: begin dac_din <= dac_data[0] ;dac_sclk <= 1‘b1;end
104                 1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31 : dac_sclk = 1‘b0;
105                 32: begin dac_sclk <= 1‘b1;end
106                 33: begin dac_cs_n <= 1‘b1;end
107                 default:; 
108             endcase
109         end
110     end
111 
112     always@(posedge clk or negedge rst_n)begin
113         if(rst_n==1‘b0)begin
114             en <= 1‘b0;
115         end
116         else if(start) begin
117             en <= 1‘b1;
118         end
119         else if(end_scl_cnt)begin
120             en <= 1‘b0;
121         end
122     end
123 
124     always@(posedge clk or negedge rst_n)begin
125         if(rst_n==1‘b0)begin
126             set_done <= 1‘b0;
127         end
128         else if(end_scl_cnt) begin
129             set_done <= 1‘b1;
130         end
131         else begin
132             set_done <= 1‘b0;
133         end
134     end
135 
136     assign dac_state = dac_cs_n;
137 
138 endmodule