为什么有些寄存器值的更新会延迟一个时钟周期变化

module counter(
        input              clk,
        input              rst_n,
        output  reg[7:0]   data_out
 
);


//reg  define
reg  [3:0] cnt;            //假设计数器每计数十次，溢满一次
reg  [2:0] lsm_cnt;   //计数器每溢满一次,lsm_cnt寄存器自加1

//parameter [7:0] num = 8‘b10110101;此句和下面两句功能等效
wire [7:0] num;       //定义一个八位数据
assign num = 8‘b10110101;   

initial  data_out <= 8‘b0000_0000; //如果此处没有给初值，那么在仿真中不知道每一位是0还是1，data_out的值将呈现高阻态为8‘dX，
                                              //只有后面case语句执行8次将寄存器的每一位都写入值后，仿真中data_out才有值显示出来
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        cnt <= 4‘d0;
    else if(cnt < 9)           //如果是发送数据则需要一个标志位去启动计数器开始计数
        cnt <= cnt + 1‘b1;
   else
        cnt <= 4‘d0;
end


always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        lsm_cnt <= 3‘d0;
    else if(cnt == 9)
        lsm_cnt <= lsm_cnt + 1‘b1;
   else 
        lsm_cnt <= lsm_cnt;
end


always@(posedge clk )begin
      if(cnt == 1)           //注意此处的作用是为了防止系统在空闲状态下还继续进行发送数据
          case(lsm_cnt)
              0: data_out[0] <= num[0]; 
              1: data_out[1] <= num[1]; 
              2: data_out[2] <= num[2]; 
              3: data_out[3] <= num[3];        
              4: data_out[4] <= num[4]; 
              5: data_out[5] <= num[5]; 
              6: data_out[6] <= num[6]; 
              7: data_out[7] <= num[7]; 
             default : data_out <= 8‘d0;
          endcase
//     else
//        data_out <= data_out;
end


endmodule

`timescale 1ns/1ps
module counter_tb;

reg sys_clk;
reg sys_rst_n;
wire [7:0] data_out;   

//例化
 counter u_counter(
         .clk(sys_clk),
         .rst_n(sys_rst_n),
           .data_out(data_out)
);
 
initial begin
    sys_clk = 1‘b1;    
   sys_rst_n = 1‘b0;
   #100;    
   sys_rst_n = 1‘b1;
   #900 $stop;
end     

always #10  sys_clk = ~sys_clk;

endmodule

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        lsm_cnt <= 3‘d0;
    else if(cnt == 9)
        lsm_cnt <= lsm_cnt + 1‘b1;
   else 
        lsm_cnt <= lsm_cnt;
end