Verilog中的三种简单触发器

module D_LOCK(D,CLK,Q,NQ);  //正边沿D触发
    output Q;
    output NQ;
    input D;
    input CLK;
    //时序赋值
    reg Q;
    assign NQ=~Q;
    
    //上升沿触发
    always @(posedge CLK)
        begin
            Q<=D;
        end
    
endmodule

//a simple testbench
module d_lock_tb();
    reg d,clk;
    wire q,nq;
    
    D_LOCK tb(
           .D(d),
           .CLK(clk),
           .Q(q),
           .NQ(nq)
    );
    
    initial
        begin
            clk=0;
         end
     always #10 clk=~clk;   //内部时钟周期20ns
     
     initial
        begin
            #20 d=0;
            #20 d=1;
            #20 d=1‘bx;
            #20 $finish;
         end
endmodule

module RS_LOCK(R,S,CLK,Q,NQ);   //边沿触发的RS触发器
    output Q;
    output NQ;
    input CLK;
    input R;
    input S;
    reg Q;
    //上升沿触发
    assign NQ=~Q;
    always@(posedge CLK)
        case({R,S})
            2‘b01: Q<=1;
            2‘b10: Q<=0;
            2‘b11: Q<=1‘bx;
            default:
        endcase
endmodule

//testbench
module rs_lock_tb();
    reg clk,r,s;
    wire q,nq;
    RS_LOCK uut(
            .R(r),
            .S(s),
            .CLK(clk),
            .Q(q),
            .NQ(nq)
            );
     initial
        begin 
            clk=0;
        end
        
    always #10 clk=~clk;    //内部时钟
    
    initial
        begin
            r=0;s=0;
            #10 r=0;s=1;
            #20 r=1;s=0;
            #20 r=1;s=1;
            #20 $finish;
         end
            
endmodule

module JK_LOCK(J,K,CLK,Q,NQ);   //边沿触发的JK触发器
    output Q;
    output NQ;
    input CLK;
    input J;
    input K;
    reg Q;
    //上升沿触发
    assign NQ=~Q;
    always@(posedge CLK)
        case({J,K})
            2‘b00: Q<=Q;
            2‘b01: Q<=0;
            2‘b10: Q<=1;
            2‘b11: Q<=~Q;
            default:Q<=Q;
        endcase
endmodule

module jk_lock_tb();
    reg clk,j,k;
    wire q,nq;
    JK_LOCK uut(
            .J(j),
            .K(k),
            .CLK(clk),
            .Q(q),
            .NQ(nq)
            );
     initial
        begin 
            clk=0;
        end
        
    always #10 clk=~clk;    //内部时钟
    
    initial
        begin
            #20 j=0;k=0;
            #20 j=0;k=1;
            #20 j=1;k=0;
            #20 j=1;k=1;
            #20 $finish;
         end
            
endmodule

module T_LOCK(T,CLK,Q,NQ);  //正边沿T触发
    output Q;
    output NQ;
    input T;
    input CLK;
    //时序赋值
    reg Q;
    assign NQ=~Q;
    
    //上升沿触发
    always @(posedge CLK)
        begin
            Q<=~T;
        end
    
endmodule

module t_lock_tb();
    reg t,clk;
    wire q,nq;
    
    T_LOCK tb(
           .T（t）,
           .CLK(clk),
           .Q(q),
           .NQ(nq)
    );
    
    initial
        begin
            clk=0;
         end
     always #10 clk=~clk;   //内部时钟周期20ns
     
     initial
        begin
            #20 t=0;
            #20 t=1;
            #20 t=1‘bx;
            #20 $finish;
　　　　　end
endmodule