FPGA-shift_ram代码

module shift_ram_3_8bit 
#(
     parameter Ram_Length = 10‘d640
)
(
    clken,
    clock,
    shiftin,
    shiftout,
    taps0x,
    taps1x);

    input      clken;
    input      clock;
    input    [7:0]  shiftin;
    output    [7:0]  shiftout;
    output    [7:0]  taps0x;
    output    [7:0]  taps1x;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
    tri1      clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

    wire [7:0] sub_wire0;
    wire [15:0] sub_wire1;
    wire [7:0] shiftout = sub_wire0[7:0];
    wire [15:8] sub_wire3 = sub_wire1[15:8];
    wire [7:0] sub_wire2 = sub_wire1[7:0];
    wire [7:0] taps0x = sub_wire2[7:0];
    wire [7:0] taps1x = sub_wire3[15:8];

    altshift_taps    ALTSHIFT_TAPS_component (
                .clock (clock),
                .clken (clken),
                .shiftin (shiftin),
                .shiftout (sub_wire0),
                .taps (sub_wire1)
                // synopsys translate_off
                ,
                .aclr ()
                // synopsys translate_on
                );
    defparam
        ALTSHIFT_TAPS_component.intended_device_family = "Cyclone IV E",
        ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
        ALTSHIFT_TAPS_component.lpm_type = "altshift_taps",
        ALTSHIFT_TAPS_component.number_of_taps = 2,
        ALTSHIFT_TAPS_component.tap_distance = Ram_Length,
        ALTSHIFT_TAPS_component.width = 8;


endmodule

//浠跨湡

`timescale 1ns/1ns
module Generate_Matrix_3x3_8bit_tb;

//system
reg clk ; //时钟或是摄像头或是vga coms_clk , vga_clk
reg rst_n ; //复位
//coms or vga
reg pre_vs ; //行有效
reg pre_hs ; //场有效
reg pre_en ; //数据有效使能
reg [7:0] pre_img_Y ; //输出的灰度数据

wire [7:0] matrixp11,matrixp12,matrixp13;
wire [7:0] matrixp21,matrixp22,matrixp23;
wire [7:0] matrixp31,matrixp32,matrixp33;
wire matrix_vs ;
wire matrix_hs ;
wire matrix_en ;


initial clk = 1;
always #5 clk = ~clk;

initial begin
rst_n = 0;
pre_vs =0 ;
pre_hs = 0;
pre_en = 0;
pre_img_Y = 0;
#51;
rst_n = 1;
pre_vs = 1;
#20;
pre_hs = 1;
#20;
pre_en = 1;
#60;
pre_en = 0;
#20;
pre_hs = 0;
#20;
pre_hs = 1;
#20;
pre_en = 1;
#60;
pre_en = 0;
#20;
pre_hs = 0;
#20;
pre_hs = 1;
#20;
pre_en = 1;
#60;
pre_en = 0;
#20;
pre_hs = 0;
#20;
pre_hs = 1;
#20;
pre_en = 1;
#60;
pre_en = 0;
#20;
pre_hs = 0;
#20;
pre_hs = 1;
#20;
pre_en = 1;
#60;
pre_en = 0;
#20;
pre_hs = 0;
$stop;
end

reg [7:0] shiftin;
always@(posedge clk or negedge rst_n ) begin
if(!rst_n)
shiftin <= ‘d1;
else if(pre_en)
shiftin <= shiftin + 1‘b1;
else
shiftin <= shiftin;
end

Generate_Matrix_3x3_8bit Generate_Matrix_3x3_8bit(
//system
.clk (clk ), //时钟或是摄像头或是vga coms_clk , vga_clk
.rst_n (rst_n ), //复位
//coms or vga
.pre_vs (pre_vs ), //行有效
.pre_hs (pre_hs ), //场有效
.pre_en (pre_en ), //数据有效使能
.pre_img_Y ( shiftin ), //输出的灰度数据
.matrixp11 (matrixp11 ),
.matrixp12 (matrixp12 ),
.matrixp13 (matrixp13 ),
.matrixp21 (matrixp21 ),
.matrixp22 (matrixp22 ),
.matrixp23 (matrixp23 ),
.matrixp31 (matrixp31 ),
.matrixp32 (matrixp32 ),
.matrixp33 (matrixp33 ),
.matrix_vs (matrix_vs ),
.matrix_hs (matrix_hs ),
.matrix_en (matrix_en )
);

endmodule