短训练序列---Verilog代码

module short_generator(

    input  wire       FFT_CLK,
    input  wire       RESET,
    input  wire       SHORT_ACK,
    output reg  [7:0] SHORT_RE,
    output reg  [7:0] SHORT_IM,
    output reg  [7:0] SHORT_INDEX,
    output reg        SHORT_DV
);


//---------------------------------------------------------------

reg[3:0] i;
reg[3:0] j;
reg [7:0] shortrom_re [15:0];
reg [7:0] shortrom_im [15:0];


always @ (negedge RESET or posedge FFT_CLK)
begin
    if(!RESET)
    begin
        i=0;
        j=0;

        SHORT_RE=0;
        SHORT_IM=0;
        SHORT_INDEX=0;
        SHORT_DV=0;

        shortrom_re[0]=8‘b00001100;
        shortrom_re[1]=8‘b11011110;
        shortrom_re[2]=8‘b11111101;
        shortrom_re[3]=8‘b00100100;
        shortrom_re[4]=8‘b00011000;
        shortrom_re[5]=8‘b00100100;
        shortrom_re[6]=8‘b11111101;
        shortrom_re[7]=8‘b11011110;
        shortrom_re[8]=8‘b00001100;
        shortrom_re[9]=8‘b00000001;
        shortrom_re[10]=8‘b11101100;
        shortrom_re[11]=8‘b11111101;
        shortrom_re[12]=8‘b00000000;
        shortrom_re[13]=8‘b11111101;
        shortrom_re[14]=8‘b11101100;
        shortrom_re[15]=8‘b00000001;

        shortrom_im[0]=8‘b00001100;
        shortrom_im[1]=8‘b00000001;
        shortrom_im[2]=8‘b11101100;
        shortrom_im[3]=8‘b11111101;
        shortrom_im[4]=8‘b00000000;
        shortrom_im[5]=8‘b11111101;
        shortrom_im[6]=8‘b11101100;
        shortrom_im[7]=8‘b00000001;
        shortrom_im[8]=8‘b00001100;
        shortrom_im[9]=8‘b11011110;
        shortrom_im[10]=8‘b11111101;
        shortrom_im[11]=8‘b00100100;
        shortrom_im[12]=8‘b00011000;
        shortrom_im[13]=8‘b00100100;
        shortrom_im[14]=8‘b11111101;
        shortrom_im[15]=8‘b11011110;
        
    end
    else 
    begin
        if(SHORT_ACK)
        begin
            if(i<=9)
            begin
                if(j<15)
                begin
                   SHORT_RE=shortrom_re[j];
                      SHORT_IM=shortrom_im[j];
                   SHORT_DV=1;
                   if(i==0&j==0)
                   begin
                        SHORT_RE=SHORT_RE>>1;
                        SHORT_IM=SHORT_IM>>1;
                   end
                   j=j+1;
                   SHORT_INDEX=SHORT_INDEX+1;
                end
                else 
                begin
                    SHORT_RE=shortrom_re[j];
                    SHORT_IM=shortrom_im[j];
                    SHORT_INDEX=SHORT_INDEX+1;
                    SHORT_DV=1;
                    j=0;
                    i=i+1;
                end
            end
            else 
            begin
                i=0;
                SHORT_RE=shortrom_re[j]>>1; 
                SHORT_IM=shortrom_im[j]>>1;
                SHORT_INDEX=SHORT_INDEX+1;
            end
        end
        else 
        begin
            i=0;
            j=0;
            SHORT_RE=0;
            SHORT_IM=0;
            SHORT_INDEX=0;
            SHORT_DV=0;
        end
    end
end

endmodule



/*


add_force {/short_generator/FFT_CLK} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps
add_force {/short_generator/RESET} -radix hex {1 0ns} {0 200ns} {1 300ns}
add_force {/short_generator/SHORT_ACK} -radix hex {0 0ns} {1 600ns}



*/